Timing Closure and the 3 Evils of Routing Congestion

Wire routing congestion negatively affects SoC development in three ways: Performance, development schedule, and manufacturing yield.

Contents: What is Routing Congestion? What causes Routing Congestion? The 3 Evils of Routing Congestion Poor Performance Longer, More Uncertain Schedules Lower Yields, Higher Costs Traditional ways to Measure and Reduce Routing Congestion Use Arteris NoC interconnect IP to Reduce Routing Congestion at the Architecture Phase
	Long paths lead to timing closure issues through increased resistance and wire delay

<<< What causes Routing Congestion?

Evil #2: Longer, More Uncertain Schedules >>>

Evil #1: Poor Performance

Failed Timing Closure and Failure to meet Design Frequency

Routing congestion makes timing closure (also known as “timing convergence”) more difficult because as the less resistive upper metal layers are quickly consumed, the EDA routing tools attempt to route long or timing-critical paths on more resistive middle and lower metal layers. The decreased cross-sectional area of the wires in the middle and lower metal layers leads to increased resistance which causes greater wire delays over longer distances.

Furthermore, as resistance in wires increases, timing closure and timing convergence issues caused by wire delays, Vdroop, poor clock skew/slew and delays in global clock distribution become more likely.

Average distances become longer because as g-cells become unavailable due to routing congestion, the EDA tools will route wires around these congested areas, increasing wire length and adding signal delay proportional to the increase in length of the wire. These signal delays contribute to the time it takes to achieve timing closure.

When target frequencies cannot be met due to timing closure issues on a certain path, the back-end designer will add repeater registers that store and hold a data value for a clock cycle, forming a multi-cycle pipelined data flow. These pipeline registers consume power and area.

Power Consumption Increases

In addition to timing closure issues, longer wire lengths and more wires lead to both dynamic and leakage power problems. Longer wires lead to increased dynamic power dissipation due to increased wire capacitance.

Also, when long wire runs require pipeline stages to address timing closure issues, the additional gates increase leakage power.

Traditional Fixes for Routing Congestion Performance Issues

When routing congestion leads to performance issues, designers attempt to mitigate these issues by adding additional metal layers, reverse scaling the metal lines, and intentionally slowing all or part of the chip down. All of these "fixes" have very expensive and negative consequences.

Add More Metal Layers?

One way to address the need for more routing resources in a system on chip is to use a fab process with more metal layers. However, this adds mask costs and process costs (millions of dollars per additional layer for NRE).

Vias are more prone to manufacturing defects and lead to yield loss Source: Via FIB cut photo from www.eaglabls.com

A process with more layers also tends to yield less because of the additional process steps. Furthermore, adding metal layers require expanding into the Z-axis by using vias between metal layers. This decreases yields yields because these vias between metal lines have a higher probability of failure than the metal lines themselves.

Vias must be as wide as the widest wire contacted

Also, expanding into the Z-axis to get around congested areas does not work because the vertical vias between metal layers are even more resistive than the wires themselves. In addition, vias have scaled more poorly across process generations than wires. Finally, via size is dictated by the width of the largest metal layer it connects to. Simply put, adding more vias uses up more area and more power.

Using more metal layers is a costly solution that eats into the profitability of a chip design.

Reverse scale the wires?

One remedy is to “reverse scale” wires by making them arbitrarily wider or taller in proportion to the previous technology node’s wires. However, wider wires create more routing congestion and taller wires create more capacitance and crosstalk, while any increase in wire profile increases power consumption and may require stronger power drivers. Reverse scaling can be implemented with design for manufacturing (DFM) tools or restrictive design rules (RDR).

Slow the Chip Down?

One method to address performance issues is to intentionally slow the chip down, reducing the frequency of all or part of the chip. This might be done when there is interconnect crosstalk within a region where a strong power driver affects neighboring wires. When this happens, a functional failure results. A way to address this is to widen the switching windows of the affected neighboring logic. In other words, slow part of the chip down. But, obviously, slowing down part of the SoC goes against the purpose of having a high performance SoC.

<<< What causes Routing Congestion?

Evil #2: Longer, More Uncertain Schedules >>>