Distributed architecture for easier routing, any topology
Arteris NoC technology allows for easier back-end routing and timing convergence because, in addition to requiring fewer wires and fewer gates than traditional interconnects, the distributed architecture of interconnect elements like switches, FIFOs, and converters allows these elements to be automatically placed and routed in small physical areas distributed throughout the chip.
Protocol conversion, packetization and serialization are performed in the network interface units (NIU), which are physically located close to each NIU’s corresponding IP block and do not create placement and routing issues.
This is in direct contrast to a traditional bus or crossbar approach where the interconnect at the physical stage is a monolithic switch or series of switches that must be squeezed between existing IP blocks, along with the commensurate tangle of congested wires.
Arteris FlexNoC provides an advantage in improving system efficiency and shortening the development cycle of smartphone SoCs.