Join our session on the physical considerations for network-on-chip developments, here in the context of RTL Architect. For a one-on-one session, book a meeting with one of our experts.
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Session Title: Building Better IP with Synopsys RTL Architect: Network-on-Chip IP Physical Explorations
Speakers: Frank Schirrmeister and Shivakumar Musini
Date: 29 March 2023
Time: 11:15 AM - 12:00 PM PT
Track: Digital Design Implementation
Description: The rapidly rising number of computing and peripheral building blocks in modern System on Chip (SoC) development is easily in the 100s. The interconnect between these blocks becomes the long pole for timing analysis and significantly contributes to power consumption. Networks-on-Chips (NoCs) have emerged as the key solution for on-chip communication and have seen a rapid rise in protocol complexity for coherent and non-coherent designs, and flows for automated RTL generation from high-level NoC topology descriptions have emerged. With the transport delay being increasingly dominated by RC wiring delay, changes in the NoC topology caused by difficulties in timing closure during the Place and Route (P&R) phase can add significant project delays. This presentation will outline a flow and methodology that uses an earlier, RTL-based estimation of timing and power consumption using Synopsys RTL Architect and will present results in time savings.
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