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    Let our experts make you an expert!

    Advanced 5-day team training using your own EDA flow and chip designs for IMMEDIATE RESULTS.

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    Become an Expert with the help of ours!

    5 days. Our experts. Your team. Your EDA flow. Your chip designs. INSTANT ROI.

Advanced IP-XACT Training

Our expert trainers provide this 3-week training to your team at your work site or at one of Arteris IP's worldwide offices. We customize this course for you and use your own EDA flows and SoC designs as we explain and implement state-of-the-art capabilities that will turn your team into chip design "rock stars".

  • Duration: Five (5) days
  • Location: On site or at Arteris IP´s premises
  • Resources: One Arteris IP Expert engineers
  • Advanced Training seminars are usually planned for groups of 4 people max

Example Training Syllabus

IP repository examples study

  • Packaging of one fixed IP
  • Packaging of one multiple parameter IP
  • Packaging of one configurable IP

Study of customer flow and requirements

  • For the automation of the interconnections, netlist generation Verilog, VHDL, …
  • Concurrent development and multiple views support with IP-XACT. How to assemble, verify and merge the IP-XACT fragments
  • Flow analysis
  • Packaging / Flow
  • Flow for RTL platform assembly: mix RTL mode
  • Flow for verification (simulators, BFMs, and more)
    • Synopsys VCS, Cadence Xcellium, Siemens ModelSim, Vera, Cadence Specman
  • Flow for synthesis
    • SDC files, timing extraction
  • Flow for Design-for-Test (DFT functions need to be identified by the packager)
    • With the objective of automating milestones of tests insertion
  • Flow for I/O MUX-ing (merge, insertion of component)
  • Directory structure modification, where to store the IP-XACT files' METADATA folders
  • Global definition for the “bus definition” or local definition
    • Update the connections
    • Update the parameters