Design & Reuse: Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
The challenges faced by design teams in managing the complexity and time-to-market pressures of modern SoC designs are advancing at a record rate. Fragmented toolchains, lack of specialized expertise, and the need for smarter workflows are just some of the challenges that integrated NoC solutions help to address. However, as the industry continues to innovate, a paradigm shift in design methodologies is necessary for companies to stay competitive.
Semiconductor Engineering: From DIY To Advanced NoC Solutions: The Future Of MCU Design
Explore the future of microcontroller design with Network-on-Chip (NoC) technology. Learn how NoC IP enhances scalability, efficiency, and functionality in advanced MCUs for automotive, IoT, and more.
EDN: SoC design: What’s next for NoCs?
NoC technology continues to advance. First-generation NoCs required manual layout and implementation. Later generations introduced physical awareness. Next-gen solutions must accelerate productivity and advance results with smart automation.
Key Observations from CES 2025 – a CMO’s Perspective
Michal Siwinski, CMO at Arteris, attended CES 2025 and collected his reflections on the major highlights, including AI’s dominance, sustainability trends, smart appliances, and how the latest NoC IP technology is helping empower the future.
SemiWiki: MCUs Are Now Embracing Mainstream NoCs
MCUs are evolving beyond traditional roles, now incorporating AI, safety, and communication support, blurring the distinction between MCUs and SoCs. Power reduction and safety compliance are driving the adoption of NoCs in MCUs, necessitating advanced network designs to support complex requirements.
Semiconductor Engineering: 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. We introduced new technology, product enhancements, and welcomed new partners and customers – together driving progress in the industry.
EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.
Semiconductor Engineering: Scaling AI Chip Design With NoC Soft Tiling
As AI workloads continue to grow in scale and complexity, NoC soft tiling offers a flexible, scalable and power-efficient solution for complex SoC and derivative designs. By simplifying integration, optimizing performance and enabling the dynamic reuse of pre-verified tiles, soft tiling is set to shape the future of AI-driven semiconductor innovation.
GSA: Get to Know the CEO with Charles Janac
Learn about the inspiring career journey of Charles Janac. Discover his advice for early-career engineers and his passion for technology.
Semiconductor Engineering: Reducing SoC Power With NoCs And Caches
The growing complexity of integrating multiple processing elements, memory systems and communication interfaces into a single SoC demands innovative solutions to optimize power efficiency. Arteris offers a comprehensive suite of IP products, including FlexNoC, Ncore and CodaCache that address these challenges.
