Frank Schirrmeister, VP Solutions & Business Development at Arteris, authored this EDN article.

September 21st, 2023

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

A recent trend is the widespread adoption of RISC-V cores, which are built upon open standard RISC-V instruction set architecture (ISA). This system is available through royalty-free open-source licenses.

Here, the utilization of network-on-chip (NoC) technologies’ plug-and-play capabilities has emerged as an effective strategy to accelerate the integration of RISC-V-based systems. This approach facilitates seamless connections between processor cores or clusters and intellectual property (IP) blocks from multiple vendors.

K. Charles Janac, President & CEO at Arteris, authored this EE Times article.

September 6th, 2023

What is the secret of humanity’s success? What has given us the ability to build wonders, such as Stonehenge in England, the Pyramids of Egypt and the Great Wall of China? Humans are small, weak and slow compared with many other animals. So what has equipped us with the capacity to spread across the globe, visit the ocean’s depths, walk on the moon and—in the not-so-distant future—travel to other planets in our solar system? The ability to think abstractly, use language to communicate complex ideas and collaborate are the determining factors.

Andy Nightingale, VP Product Management & Marketing at Arteris, authored this Electronic Design article.

August 24th, 2023

Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.

Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I2C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors

Frank Schirrmeister, VP Solutions & Business Development at Arteris, authored this Semiconductor Engineering article.

August 24th, 2023

While writing last month’s blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020 or earlier, but I was too close to the deadline to sit down and make orderly updates to some of the charts. Working day-to-day in the area of SoC integration and networks-on-chips (NoCs), the classic chart based on Karl Rupp’s now 50 years of processor data that overlays the Moore’s law transistors with single-thread performance, processor frequency, typical power, and the number of processor cores is relevant, but not quite perfect. Yes, processor cores are essential, but there are many other types of silicon IP blocks (SIP) to be connected using NoCs and integrated using what we at Arteris call “SoC Integration Automation.”

So, I looked for the relevant source data and developed some new visualizations.

Daniel Payne from SemiWiki, authored this article about Arteris.

August 16th, 2023

I met up with Andy Nightingale, VP Product Marketing and Michal Siwinski, Chief Marketing Officer of Arteris at #60DAC for an update on their system IP company dealing with SoCs and chiplet-based designs. SemiWiki has been blogging about Arteris since 2011, and the company has grown enough in those 12 years to have an IPO, see their IP used in 3 billion+ SoCs, attract 200+ customers and have 675+ SoC design starts. Their IP is used for creating a Network-on- Chip (NoC) through interconnect IP and interface IP, plus they have EDA software used for SoC integration automation.

Andy Nightingale,  VP Product Management & Marketing at Arteris, authored this EDN article.

July 26th, 2023

Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Functional IP blocks connect to the network-on-chip (NoC) via sockets. In the case of an initiator IP, the socket serializes and packetizes the data generated by the IP, assigns an ID to the packet, and dispatches it into the network. When the packet arrives at its destination IP, the associated socket extracts the data from the packet and transforms it into the protocol required by the IP. A large number of packets can be in flight throughout the network at any given time.

Frank Schirrmeister, VP Solutions & Business Development at Arteris, authored this Semiconductor Engineering article.

July 27th, 2023

As Silicon Valley is in the midst of the heat wave the world is experiencing, the recent Design Automation Conference and its exhibition discussed hot technologies. Three megatrends defined the current situation – artificial intelligence (AI), chiplets, and integration. To me, the more exciting aspect of DAC was the discussion of what is ahead for EDA in the decade to come, and for that, the keynotes and vision talks inspired but also gave no succinct unified clear answer in my mind.

Pascal Chauvet,  Senior Director SoC Integration Automation at Arteris, authored this EDACafe article.

July 19th, 2023

Today’s multi-billion-transistor system-on-chip (SoC) devices are composed of hundreds of functional intellectual property (IP) blocks. The creation of SoCs is typically a combination of acquired IP blocks from trusted third-party vendors and a few internally developed IP blocks containing the secret sauce that differentiates the design from competitive offerings.

Third-party IPs may include central processing units, graphics processing units, memory subsystems, dynamic memory access controllers, external memory controllers and communications functions such as Ethernet, USB and MIPI. Internally developed IPs may include hardware accelerators and machine learning inference engines.

The different IP blocks must be carefully integrated for the device to work properly. SoC integration is the process of gathering all of these IPs together to form a complete device, but this involves much more than simply plugging them into each other like the pieces of a jigsaw puzzle. SoC integration is challenging, involves hidden complexity and is prone to errors.

Designers consistently integrate diverse content from multiple sources while collaborating with teams across various sites with limited cross-team synergy. A large variety of their tasks necessitates a significant amount of manual operations. Because of these challenges, designs are delayed and schedules slip, leading to missed time-to-market and time-to-revenue goals.

Bernard Murphy authored this SemiWiki article about Arteris

July 19th, 2023

I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees of dependable system performance. An ABS design which might get bogged down in traffic under only 0.1% of scenarios is of no use to anyone. That said, meeting target PPA goals remains a core benchmark for successful designs. PPA is still, presuming an architectural design and IP which should be able to meet those goals, a primary source of risk for high-complexity SoC designs in advanced processes.

Frank Schirrmeister, VP Solutions & Business Development at Arteris talks to Ann Mutschler from Semiconductor Engineering in this video interview.

July 17th, 2023

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella, including everything from memory tagging to RISC-V and optimism about new talent.

Frank Schirrmeister, VP Solutions & Business Development at Arteris authored this Semiconductor Engineering article.

July 6th, 2023 - by Frank Schirrmeister

This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call “Electronic Design Automation” (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. For me, this will be the 25th DAC that I am attending. During my first DAC in 1998, Gary Smith had just coined the term “Electronic System Level” (ESL), and High-Level Synthesis was the year’s hot topic. The industry has made great strides since then, albeit not always in the predicted direction. High-level synthesis has “simply” become the front end for digital implementation flows. It has never grown up to synthesize many whole chips, but it is these days critical to block development, porting between semiconductor technologies, and Engineering Change Order (ECO) management.

Andy Nightingale, VP of Product Management & Marketing at Arteris authored this Design & Reuse article.

June 30th, 2023 - by Andy Nightingale

Today's system-on-chip (SoC) devices may be composed of hundreds of functional blocks known as intellectual property (IP) blocks. Each of these IPs can contain hundreds of millions of transistors. Standard IPs like processors, memory, codecs and communication functions are usually acquired from third-party vendors. By procuring conventional IP, design teams can focus on the in-house development of special functions like inference engines for artificial intelligence (AI) and machine learning (ML) applications. These internally developed IPs are the "secret sauce" that will differentiate this SoC from competitive offerings.

Bernard Murphy authored this SemiWiki article on Service Level Risk in SoC Design.

June 21st, 2023 - by Bernard Murphy

Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum service level agreement (SLA). A printer display may work fine most of the time yet will intermittently corrupt the display. Or the nav system in your car intermittently fails to signal an upcoming turn until after you pass the turn. These are traffic (data) related problems. Conventional performance metrics only ensure that the system will perform as expected under ideal conditions; SLA metrics set a minimum performance expectation within specified traffic bounds. OEMs ultimately care about SLAs, not STAs. Meeting/defining an SLA is governed by interconnect design and operation.

Guillaume Boillet, Senior Director of Product Management at Arteris, authored this EDN article.

June 7th, 2023 - by Guillaume Boillet

In the not-so-distant past, system-on-chip (SoC) devices were relatively simple compared to today’s offerings. Early SoCs typically consisted of 10 to 20 intellectual property (IP) blocks, each generally composed of around 10,000 to 50,000 logic gates. Most of these IPs, including the processor and peripheral functions, were licensed from third-party vendors. Developers normally created only one or two IPs containing the “secret sauce” that differentiated their SoC from other competitive offerings.

Andy Nightingale, VP Product Management & Marketing at Arteris, spoke to EE Journal's Amelia Dalton on the fish fry podcast.

March 26th, 2023 - by Andy Nightingale

Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs. We also discuss the details of Arteris’ FlexNoC 5 Physically Aware Network-on-Chip IP, and how a physically aware NoC can not only help you address your PPA goals but also get you to physical convergence faster. Also this week, I investigate a newly discovered exoplanet called LP 791-18d.

Frank Schirrmeister, VP Solutions and Business Development at Arteris, authored this Semiconductor Engineering article.

June 1st, 2023 - by Frank Schirrmeister

The recent AutoSens conference in Detroit left me questioning whether I should turn in my driver’s license. The answer the attending OEMs gave to all the discussions about the advantages of RGB cameras, ultrasound, radar, lidar, and thermal sensors was a unanimous “We probably need all of them in some form of combination” to make autonomy a reality in automotive. Together, these sensors are much better than my eyes and ears. Technology progress is speedy in Automated Driving Assistance Systems (ADAS) and autonomous driving, but we are not there yet holistically. So I am keeping my license for some more time.

Bernard Murphy authored this SemiWiki article on Interconnect Strategy.

May 9th, 2023 - by Bernard Murphy

“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions you made on a first-generation design when implementing follow-on designs. Or face major rework to correct for issues you hadn’t foreseen. Making optimum architecture decisions for the series at the outset is key. Will it support replicating a major subsystem allowing more channels in premium versions, for more sensors or more video streams? Can the memory subsystem scale to support increased demand? Careful planning and modeling, checking target bandwidths and latencies is a necessary starting point. However architectural feasibility alone may not be sufficient to ensure scalability for one critical component – the interconnect between the function blocks in the design.

Frank Schirrmeister, VP Solutions and Business Development at Arteris, authored this Semiconductor Engineering article.

May 4th, 2023 - by Frank Schirrmeister

That was the overarching question a group of 180 experts discussed last week at the ISO 26262 & SOTIF conference for four days during #FuSaWeek2023 in Berlin. “How Safe is Safe Enough” is also the title of Prof. Koopman’s book from September 2022. I mentioned him in my blog “Are We Too Hard On Artificial Intelligence For Autonomous Driving?” Prof. Koopman was referenced often in Berlin, and he will give the Thursday keynote titled “Defining Safety for Shared Human/Computer Driver Responsibility” next week at AutoSens Detroit.

Arteris President & CEO K. Charles Janac, authored this EE Times article.

April 26th, 2023 - by K. Charles Janac

Consider that there were more than 38,824 automotive fatalities and 115,000 injury accidents in 2020 in the United States alone, according to the U.S. Department of Transportation. Additionally, Bankrate estimates that the economic cost is $474 billion, which includes wage loss, medical and administrative expenses, motor vehicle damage and uninsured costs. The opportunity to prevent 20% to 50% of these tragedies by developing automated driving technology to reduce the loss of valuable lives and the associated economic impact is a necessary goal.

Bernard Murphy authored this article about Arteris on SemiWiki.

April 6th, 2023 - by Bernard Murphy

In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability with no downsides. Then the easy wins became less easy. More advanced processes continued to deliver higher gate counts per unit area but gains in performance and power started to flatten out. Since our expectations for innovation didn’t stop, hardware architecture advances have become more important in picking up the slack.