Arteris Articles

SemiWiki: The Zen of Auto Safety - a Path to Enlightenment

Kurt Shuler, VP of Marketing and Stefano Lorenzini, Functional Safety Manager at Arteris IP, share stories with Bernard Murphy (SemiWiki) to help you chill. Safety is critical, but that’s doesn't mean you have to panic. 

The Zen of Auto-Safety - a Path to Enlightenment

July 7, 2021 - Bernard Murphy

Safety is a complex topic, but we’re busy. We take the course, get the certificate. Check, along with a million other things we need to do. But maybe it’s not quite that simple. I talked recently with Kurt Shuler (VP of marketing) and Stefano Lorenzini (functional safety manager) at Arteris IP and concluded that finding enlightenment in safety is more of a journey than a destination. I’m going to share with you a few stories they told me which highlight this journey. Because journeys / stories are my favorite way to share an idea.
Topics: SoC NoC network-on-chip semiconductor automotive arteris ip semiwiki functional safety manager RTL FMEDA noc interconnect hybrid AI SoCs Tier 1s AI/ML AoU assumptions of use

Arteris IP Has a New Updated Website!

Arteris IP has a new website!

Topics: SoC NoC ArterisIP noc interconnect ML/AI IP market SoC IP chip design ip deployment

EDA Cafe: Arteris IP Extends IP-XACT to UVM Testbenches

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article for EDA Cafe:

Arteris IP Extends IP-XACT to UVM Testbenches

July 2, 2021 - By Vincent Thibaut


To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

Topics: SoC NoC arteris ip verification ip-xact UVM ip deployment IPD testbench assembly DUT SoC testbenches vincent thibaut VIPs UVM testbenches

Semiconductor Engineering: New Design Approaches For Automotive

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

New Design Approaches For Automotive

July 1st, 2021 - By Ann Steffora Mutschler

OEMs steer toward executable specs using model-based systems engineering.


“If you’re creating an anti-lock braking system or a windshield washer or something like that, it’s relatively simple and you don’t have to spend much time with these tools to be able to come up with that model,” said Kurt Shuler, vice president of marketing at Arteris IP. “But once you get to something really complex like a system on chip — just like with creating SystemC models or the like — you could spend more time than you would on the RTL, or on writing the specs for the RTL, the requirements and use cases for the specs for the RTL, or a SysML model.”

Topics: SoC NoC ISO 26262 ArterisIP SystemC semiconductor engineering arteris ip RTL kurt shuler SoC assembly SysML MBSE