Arteris Articles

Semiconductor Engineering: Optimizing NoC-Based Designs

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Optimizing NoC-Based Designs

May 5th, 2022 - By Paul Graykowski

Further optimization of RTL repartitioning with switching from crossbar interconnects to NoCs.

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are resulting in a new breed of SoCs. These fields demand designs that are maximized for both power and performance efficiency. Designers are finding that networks-on-chip (NoCs) provide the enabling technology to meet this demand and are accelerating the move away from crossbar interconnect technology.

Learn more about Arteris IP Deployment Technology Products .

 

Topics: network-on-chip timing closure ADAS semiconductor engineering latency bandwidth SoCs congestion logic RTL data centers AI/ML NoCs floorplan Arteris IP (AIP) Paul Graykowski partitioning physical design crossbar interconnect robotics

Electronic Design Article: Making ISO 26262 Traceability Practical


This Electronic Design article, 'Making ISO 26262 Traceability Practical', covers Arteris IP's Harmony Trace in this piece authored by Paul Graykowski, Senior Technical Marketing Manager. 

March 4 , 2021 - By Paul Graykowski

The ISO 26262 standard states that functional-safety assessors should consider if requirements management, including bidirectional traceability, is adequately implemented. The standard doesn’t specify how an assessor should go about accomplishing this task. However, it’s reasonable to assume that a limited subset of connections between requirements and implementation probably doesn’t rise to the expectation.

 

For more information about Arteris Harmony Trace please visit: https://www.arteris.com/harmony-trace-design-data-intelligence

 

Topics: NoC functional safety ISO 26262 network-on-chip autonomous vehicles ip-xact SoCs AI chips EDA electronic design traceability Arteris IP (AIP) Arteris Harmony Trace Paul Graykowski HSI PLM ALM

Semiconductor Engineering: Where Do Memory Maps Come From?

Guillaume Boillet, Senior Director of Product Management at Arteris IP authored this Semiconductor Engineering article:

Where Do Memory Maps Come From?

March 3rd, 2022 - By Guillaume Boillet

Ensuring software can accurately address hardware.


A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears, but the reality is much more involved. The union of hardware (HW) and software (SW) demands both planning and compromise. The outcome of this merger will not be fully realized until the magical day when the system comes to life.

To learn more about SoC and Hardware/Software Interface (HSI) Development, please download this datasheet:  SoC & Hardware / Software Interface (HSI) Development Datasheet 

 

Topics: software network-on-chip power time to market semiconductor engineering arteris ip hardware SoCs EDA Guillaume Boillet NoCs Arteris IP (AIP) HSI addresses embedded firmware memory map

SemiWiki: An Ah-Ha Moment for Testbench Assembly

Bernard Murphy (SemiWiki) gets an update from Arteris IP.

An Ah-Ha Moment for Testbench Assembly 

February 28, 2022 - Bernard Murphy

Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing their energy in learning UVM. UVM is fine, so why do we need to talk about anything different? That’s the forest and trees thing. We don’t need to change the way we define testbenches – the behavior and (largely) the top-level structure. But maybe there’s a better way to assemble that top level through a more structured assembly method than through hand-coding or ad-hoc scripting. Still built on UVM at leveraging the standardization benefits of IP-XACT for assembly around VIPs.
 
Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL UVM noc interconnect test bench assembly Arteris IP Harmony Trace Paul Graykowski Jama software SoC verification Magillem UTG UVM Testbench Generator Arteris (AIP)