Arteris Articles

Semiwiki: Taming Physical Closure Below 16nm

Arteris CEO Joins Bernard Murphy for this Semiwiki article.

Taming Physical Closure Below 16nm

 January 30th, 2023 - By Bernard Murphy

Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design. Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and route technologies and teams are not the problem – they are as capable as ever. The problem lies in increasingly strong coupling between architectural and logic design and physical implementation. Design/physical coupling at the block level is well understood and has been addressed through physical synthesis. However, below 16nm it is quite possible to design valid SoC architectures that are increasingly difficult to place and route, causing project delays or even SoC project cancellations due to missed market windows.

Topics: SoC IP System-on-Chip NoC network-on-chip SemiWiki PPA AIP physical design Charlie Janac Arteris

EDACafé: Industry Predictions for 2023 – Arteris

Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this EDACafé article:

EDACafé Industry Predictions for 2023 – Arteris

 January 24th, 2023 - By Frank Schirrmeister

Discover this article by Arteris’ Frank Schirrmeister on the trends that will shape 2023. See how the ever-increasing demand for higher performance and power efficiency will drive the development of new materials, designs and manufacturing processes.

Topics: SoC IP System-on-Chip NoC network-on-chip automotive data center 5G AIP Arteris AI/ML EDACafé Frank Schirrmeister

Semiwiki:The Impact of Using a Physically Aware NoC with Charlie Janac Podcast

Arteris CEO Joins SemiWiki’s Daniel Nenni on Semiconductor Insiders Podcast

Podcast EP138: The Impact of Using a Physically Aware NoC with Charlie Janac

 January 20th, 2023 - By Daniel Nenni

Tune into Podcast EP138: The Impact of Using a Physically Aware NoC with Arteris CEO, Charlie Janac, as he discusses the benefits of using network-on-chip, or NoC IP on several types of design projects. Discover the tangible benefits of using physical awareness for the NoC and how to set up this valuable capability to streamline SoC design, get to market faster and achieve better SoC economics with lower risk.

Topics: SoC System-on-Chip NoC network-on-chip SemiWiki AIP Charlie Janac Arteris

Semiconductor Engineering: Shortening Network-on-Chip Development Schedules Using Physical Awareness

Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this Semiconductor Engineering article:

Shortening Network-on-Chip Development Schedules Using Physical Awareness

 January 5th, 2023 - By Frank Schirrmeister

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC) architectures and the dependencies on the size and placement of other IP blocks, they are susceptible to physical effects.

Topics: SoC System-on-Chip NoC network-on-chip power Semiconductor Engineering security physical design design chip test