Bernard Murphy authored this SemiWiki article on Interconnect Strategy.

May 9th, 2023 - by Bernard Murphy

“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions you made on a first-generation design when implementing follow-on designs. Or face major rework to correct for issues you hadn’t foreseen. Making optimum architecture decisions for the series at the outset is key. Will it support replicating a major subsystem allowing more channels in premium versions, for more sensors or more video streams? Can the memory subsystem scale to support increased demand? Careful planning and modeling, checking target bandwidths and latencies is a necessary starting point. However architectural feasibility alone may not be sufficient to ensure scalability for one critical component – the interconnect between the function blocks in the design.

Frank Schirrmeister, VP Solutions and Business Development at Arteris, authored this Semiconductor Engineering article.

May 4th, 2023 - by Frank Schirrmeister

That was the overarching question a group of 180 experts discussed last week at the ISO 26262 & SOTIF conference for four days during #FuSaWeek2023 in Berlin. “How Safe is Safe Enough” is also the title of Prof. Koopman’s book from September 2022. I mentioned him in my blog “Are We Too Hard On Artificial Intelligence For Autonomous Driving?” Prof. Koopman was referenced often in Berlin, and he will give the Thursday keynote titled “Defining Safety for Shared Human/Computer Driver Responsibility” next week at AutoSens Detroit.

Arteris President & CEO K. Charles Janac, authored this EE Times article.

April 26th, 2023 - by K. Charles Janac

Consider that there were more than 38,824 automotive fatalities and 115,000 injury accidents in 2020 in the United States alone, according to the U.S. Department of Transportation. Additionally, Bankrate estimates that the economic cost is $474 billion, which includes wage loss, medical and administrative expenses, motor vehicle damage and uninsured costs. The opportunity to prevent 20% to 50% of these tragedies by developing automated driving technology to reduce the loss of valuable lives and the associated economic impact is a necessary goal.

Bernard Murphy authored this article about Arteris on SemiWiki.

April 6th, 2023 - by Bernard Murphy

In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware delivered improved performance/area/power metrics every year, allowing software to expand in complexity and deliver more capability with no downsides. Then the easy wins became less easy. More advanced processes continued to deliver higher gate counts per unit area but gains in performance and power started to flatten out. Since our expectations for innovation didn’t stop, hardware architecture advances have become more important in picking up the slack.

Steven Leibson from EE Journal authored this article with quotes from Frank Schirrmeister, VP of Solutions and Business Development at Arteris.

March 29th, 2023 - by Steven Leibson

Network on Chip (NOC) IP has been around for a while. I wrote an article about academic research papers on NOCs presented at the seventh annual International Symposium on System-on-Chip conference held in Tampere, Finland in late 2005. NOCs were the conference’s theme back then and the jury was out on using NOCs to interconnect large IP blocks, including processors, network controllers, and memory on SoCs. NOCs introduce overhead that wasn’t particularly welcome back in 2005. Today, it’s a different story.

Andy Nightingale, VP Product Management & Marketing at Arteris, authored this EDN article.

March 13th, 2023 - by Andy Nightingale

A system-on-chip (SoC) containing a million transistors was considered a large device in the not-so-distant past. Today, SoCs commonly contain up to a billion transistors. Consider, for example, the recent case study with SiMa.ai and its new machine learning (ML) chip called MLSoC; it provides effortless machine learning at the embedded edge.

Spencer Chin, Senior Editor for Design News, authored this Design News Article on Arteris' FlexNoC 5.

March 6th, 2023 - By Spencer Chin

As with other designs, engineers looking to create system-on-chips are seeking to accelerate the design process. Arteris, Inc., a provider of system IP, has launched its Arteris FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP. FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC.

Andy Nightingale, VP Product Management & Marketing at Arteris, talks with Ed Sperling in this Semiconductor Engineering video.

March 6th, 2023 - By Ed Sperling

More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product marketing at Arteris IP, talks about how to shrink the NoC area, improve security, and reduce time to market.

Andy Nightingale, VP Product Management & Marketing at Arteris, talks with William G. Wong in this Electronic Design video.

February 22nd, 2023 - by William G. Wong

Arteris IP has released FlexNoC 5, a network-on-chip (NoC) IP configuration tool, designed to improve system-on-chip (SoC) designs and streamline the design cycle. I spoke with Arteris IP's VP of Product Development, Andy Nightingale, about the company's physically aware NoC IP (see video above). The system is designed to provide an optimized, working NoC layout while significantly reducing the design-cycle time.

Majeed Ahmad, Editor-in-Chief of EDN, authored this article about Arteris' FlexNoC 5.

 February 23rd, 2023 - By Majeed Ahmad

The network-on-chip (NoC) technology, which connects IP blocks in highly complex system-on-chip (SoC) designs, has ascended to the next logical level by becoming physically aware. According to Andy Nightingale, VP of product marketing at Arteris, that accelerates the exploration of the needed space to achieve an optimal NoC topology at the front-end and speeds up timing closure at the back-end. Arteris has unveiled its next-generation interconnect IP, FlexNoC 5, which it calls the first physically aware NoC technology. It’s aimed to allow SoC architecture teams, logic designers, and integrators to incorporate physical constraint management and achieve faster physical convergence over manual refinements with fewer iterations from the layout team.

Frank Schirrmeister, VP of Solutions and Business Development at Arteris, authored this Semiconductor Engineering article.

 March 2nd, 2023 - By Frank Schirrmeister

You may know about my fascination with ecosystems if you have followed my writing. It is only fitting that I am writing this Blog in Munich (shiver, it’s cold), where I attended the GSA McKinsey workshop on “Distributed E/E Architectures and Zonal Computing.” This workshop had attendees from semiconductor foundries, EDA vendors, IP vendors, Tier 1 Semis, Tier 2 Integrators, software vendors, and automotive OEMs. Earlier this week, we announced our extension into the processor ecosystem with our work with SiFive on RISC-V on Edge AI, just months after we had announced our partnership with Arm on automotive applications. As you can tell, we are neutral and work with all processor vendors equally.

Frank Schirrmeister, VP of Solutions and Business Development at Arteris, authored this Semiconductor Engineering article.

February 22nd, 2023 - By Frank Schirrmeister

As they say, while history may not repeat itself, it sure rhymes. In 2015, I wrote the blog “Why Implementation Matters To System Design And Software.” At the time, I mused that while abstraction is essential in system design, it has limitations that users must consider. Critical decisions, such as those regarding power and performance, require more accuracy than can be feasibly abstracted. But it takes time to get to this increased accuracy. Power analysis driven by RTL-based emulation would provide more accurate power predictions when considering implementation effects seen when modeling semiconductor technology more accurately.

Andy Nightingale, VP of Product Management at Arteris, authored this Design & Reuse article.

 February 23rd, 2023 - By Andy Nightingale

Today’s system-on-chip (SoC) designs continue to grow in capacity and complexity. The only way to continue developing components of this class is by increasing the sophistication of the design, implementation and verification tools while simultaneously increasing levels of automation. The launch of the latest generation of network-on-chip (NoC) IP, FlexNoC 5, from Arteris addresses all these issues.

Andy Nightingale, VP of Product Management at Arteris, authored this EDN article.

Why network-on-chip IP in SoC must be physically aware

 February 10th, 2023 - By Andy Nightingale

Today, multicore system-on-chip (SoC) designs can be composed of hundreds of IP blocks, typically containing up to ten million logic gates. One way for SoC developers to create devices of this complexity is to make use of proven IP blocks provided by trusted third-party vendors. There’s no point in devoting thousands of hours to reinventing a USB 3.2 Gen x interface, for example, when it is already available as off-the-shelf IP. Instead, engineers can focus their efforts on creating their own internal IP that will differentiate their SoC from any competitive offerings.

Arteris CEO Joins Bernard Murphy for this Semiwiki article.

Taming Physical Closure Below 16nm

 January 30th, 2023 - By Bernard Murphy

Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design. Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and route technologies and teams are not the problem – they are as capable as ever. The problem lies in increasingly strong coupling between architectural and logic design and physical implementation. Design/physical coupling at the block level is well understood and has been addressed through physical synthesis. However, below 16nm it is quite possible to design valid SoC architectures that are increasingly difficult to place and route, causing project delays or even SoC project cancellations due to missed market windows.

Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this EDACafé article:

EDACafé Industry Predictions for 2023 – Arteris

 January 24th, 2023 - By Frank Schirrmeister

Discover this article by Arteris’ Frank Schirrmeister on the trends that will shape 2023. See how the ever-increasing demand for higher performance and power efficiency will drive the development of new materials, designs and manufacturing processes.

Arteris CEO Joins SemiWiki’s Daniel Nenni on Semiconductor Insiders Podcast

Podcast EP138: The Impact of Using a Physically Aware NoC with Charlie Janac

 January 20th, 2023 - By Daniel Nenni

Tune into Podcast EP138: The Impact of Using a Physically Aware NoC with Arteris CEO, Charlie Janac, as he discusses the benefits of using network-on-chip, or NoC IP on several types of design projects. Discover the tangible benefits of using physical awareness for the NoC and how to set up this valuable capability to streamline SoC design, get to market faster and achieve better SoC economics with lower risk.

Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this Semiconductor Engineering article:

Shortening Network-on-Chip Development Schedules Using Physical Awareness

 January 5th, 2023 - By Frank Schirrmeister

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC) architectures and the dependencies on the size and placement of other IP blocks, they are susceptible to physical effects.

Michael Frank, VP and Chief Architect, and Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this Semiconductor Engineering article:

When Does My SoC Design Need A NoC?

 December 1st, 2022 - By Michael Frank and Frank Schirrmeister

Excluding the simplest offerings, almost every modern system-on-chip (SoC) device will implement its on-chip communications utilizing a network-on-chip (NoC). Some people question whether it is necessary to use a NoC or whether a more basic approach would suffice.

Frank Schirrmeister, VP Solutions & Business Development at Arteris IP authored this Semiconductor Engineering article:

Are We Too Hard On Artificial Intelligence For Autonomous Driving?

 November 3rd, 2022 - By Frank Schirrmeister

Making sense of the many automotive safety standards and requirements.

I recently attended and presented at Detroit’s “Implementation of ISO 26262 & SOTIF” conference. Its subtitle was “Taking an Integrated Approach to Automotive Safety.” After three days, my head was spinning with numbers of ISO/SAE and other standards. And at the end of day two, after yet another example that tricked autonomous driving prototypes into behaving wrongly, I sighed and asked whether anybody else would feel bad for these AIs. It feels like we ask AI to do much more than any human being could ever do. My question got some chuckles but caused some honest discussion about how to quantify autonomous driving capabilities.

Download Frank's presentation "FMEDA Automation for Scalability and Reuse in Complex System on Chips" presented at this year's "Implementation of ISO 26262 & SOTIF" conference in Detroit.