Semiconductor Engineering: A Network-on-Chip (NoC) For Multi-Die Devices
- Ashley Stevens
- < 1 min read
The semiconductor industry is rapidly transitioning from monolithic SoCs to chiplet-based architectures. At the same time, AI workloads are evolving beyond cloud inference into physical AI: systems that perceive, reason, and act in the real world. Autonomous vehicles, industrial robots, humanoid robots, drones, and intelligent manufacturing systems all require continuous, high-volume data flow between heterogeneous compute engines.
However, these two trends expose a weakness in today’s die-to-die communication architectures. While coherent interconnect protocols have been highly successful for processor-centric systems, they are fundamentally mismatched to the traffic patterns generated by modern AI accelerators.
As a result, a new approach is needed that involves transporting the native packetized traffic of the NoC directly across die boundaries using a stable, invariant interface.
Physical AI changes the nature of on-chip communication
Traditional processors are dominated by memory accesses, synchronization, and cache coherence. Physical AI systems are different. A modern automotive compute platform may simultaneously execute:
- Multiple camera processing pipelines
- Radar and lidar signal processing
- Sensor fusion
- AI perception networks
- Localization and mapping
- Path planning
- Functional safety monitoring
- Vehicle actuator control
To read the full article on Semiconductor Engineering, click here.
