Synopsys announced their new cache coherent subsystem verification solution which integrates with Arteris Ncore: Synopsys Delivers Industry's First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect.
Kurt Shuler, on Tue, May 24, 2016 @ 03:00 PM
Synopsys announced their new cache coherent subsystem verification solution which integrates with Arteris Ncore: Synopsys Delivers Industry's First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect.
Kurt Shuler, on Tue, May 24, 2016 @ 01:37 PM
Arteris Ncore has been featured in a detailed article in AnandTech by Andrei Frumusanu titled, "Arteris Announces Ncore Cache-Coherent Interconnect." You can see the big link in the top left of the home page or read it directly at http://anandtech.com/show/10339/arteris-announces-ncore-cachecoherent-interconnect.
Kurt Shuler, on Tue, May 17, 2016 @ 04:37 AM
Here's a good article by Ann Steffora Mutschler that describes some of the issues of implementing hardware cache coherency using cache coherent interconnects. Neil Parris from ARM is quoted, as am I.
Here's the link to the full article: http://semiengineering.com/coherency-cache-and-configurability/
Kurt Shuler, on Tue, May 03, 2016 @ 04:05 PM
SemiEngineering has published a Tech Talk video I did with editor Ed Sperling about the ISO 26262 standard and advanced driver assistance systems (ADAS).
Want to know the difference between ISO 26262 ASIL B and ASIL D? Then view it at: http://semiengineering.com/tech-talk-adas/