Arteris Articles

SemiWiki: CEO Interview: Charlie Janac of Arteris IP

Charlie Janac, president and CEO at Arteris IP interviewed by Daniel Nenni in this new SemiWiki blog:

CEO Interview: Charlie Janac

August 28, 2020 - By Daniel Nenni

Why is on-chip interconnect important for SoC innovation?
System-on-chip architectures are rapidly changing because we are moving from “data processing” chips to SoCs able to execute “decision making” models. The on-chip interconnect is the logical and physical means to create the SoC architecture so the importance of the network-on-chip (NoC) interconnect has increased as the need for architectural innovation has grown.

What developments do you see that Arteris IP is able to address?
We’re at a very exciting time because an important ingredient for performant SoCs has clearly become the on-chip interconnect and all the SoC architectural changes by our customers are influencing our technology development.

Topics: SoC network-on-chip semiconductor automotive Ncore cache coherency FlexNoC networks AI semiwiki charlie janac noc interconnect ceo data processing superscalers

Semiconductor Engineering: What Happened To Execute-In-Place?

Michael Frank, Fellow and Chief Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

What Happened To Execute-In-Place?

August 25th, 2020 - By Bryon Moyer

The concept as it was originally conceived no longer applies. Here’s why.

“Demand-paging virtual memory is nothing else than a cache,” noted Michael Frank, fellow and chief architect at Arteris IP . But then Android came available for free, unlike the planned OSes. So the strategy changed from one of demand-paging to moving the entire code base from flash to DRAM, and then using the SRAM cache mechanism to further manage instruction access times — all in the interest of lower cost.
Frank also stated, “My definition of execute in place is where you do not have an address change, where you execute in a cached way, and your original source of the code or the data is still at the same address that you are executing at.”
Topics: SoC NoC technology semiconductor engineering soc architecture AI cache DRAM noc interconnect IP market SRAM MCUs

SemiWiki: Interconnect Basics: Wires to Crossbar to NoC

Kurt Shuler shares with Bernard Murphy an introduction to interconnect topologies, a useful primer to anyone who thinks of interconnect as “just wires” in this new SemiWiki blog:

Interconnect Basics: Wires to Crossbars to NoC

August 21, 2020 - By Bernard Murphy

To many of us, if we ever think about interconnect on an SoC, we may think delay, power consumption, congestion, that sort of thing. All important points from an implementation point of view, but what about the functional and system implications? In the early days, interconnect was very democratic, all wires more or less equal, connecting X to Y wherever needed. If you had a data bus, you’d route that more carefully to ensure roughly equal delays for each bit, which works pretty well when you don’t have a lot of on-chip functions. But there’s more to it than that. This blog is a quick introduction to interconnect basics.

Topics: SoC network-on-chip crossbar semiconductor Ncore FlexNoC networks AI semiwiki kurt shuler noc interconnect NoC layer

Semiconductor Engineering: From Cloud To Cloudlets

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

From Cloud To Cloudlets

August 17th, 2020 - By Ed Sperling

Why the intersection of 5G and the edge is driving a new compute model.

In the U.S., they’re using the higher S band, which is used for things like radar,” said Kurt Shuler, vice president of marketing at Arteris IP. “In other parts of the world, they’re using much lower frequency bands, which is more useful. It could replace or augment what they already have on a cell phone. So in the United States, the use cases are largely around things like factories and automotive. Overseas, that’s much different.
One such use case involves industrial robots, Shuler said, where microcell chipsets are used to control and monitor the activities of those robots. Most of those are fixed robots, but response time is critical.
Topics: SoC automotive NoC technology semiconductor engineering soc architecture bandwidth kurt shuler noc interconnect chipsets 5G IP market communications industrial robots

Semiconductor Engineering: Virtualization In The Car

Stefano Lorenzini, Functional Safety Manager at Arteris IP is quoted in this new article in Semiconductor Engineering:

Virtualization In The Car

August 6th, 2020 - By Ann Steffora Mutschler

How and why abstraction layers are becoming essential in automotive design.

“It’s a way to create multiple virtual instantiations of the same hardware, and every instance is virtually dedicated to a specific product or software or application,” said Stefano Lorenzini, functional safety manager at Arteris IP . “The hypervisor is a bare-metal operating system that runs directly on the hardware and creates an intermediate layer with respect to other application or software programs that are running on top. So if you want to look to the architecture from the top to the bottom, you see the application, then you see the hypervisor, and then you see the hardware layer. The hypervisor is the thing that creates this illusion to the application that every resource of the SoC is dedicated to them.”
Topics: SoC automotive autonomous vehicles NoC technology semiconductor engineering soc architecture AI ASIL D functional safety manager noc interconnect IP market automotive electronics