Arteris Articles

Semiconductor Engineering: Computing Where Data Resides

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new Semiconductor Engineering article:

Computing Where Data Resides

March 29th, 2021 - By Ann Steffora Mutschler

Computational storage approaches push power and latency tradeoffs.

“Ten years ago solid state drives were new,” said Kurt Shuler, vice president of marketing at Arteris IP. “There really wasn’t anything like an enterprise SSD. There were little microcontrollers running on platter-type hard drives. That was where semiconductors were then. Since that time, so much has changed. A lot of startups were doing really sophisticated SSD controllers, and the problem initially was that NAND flash consumes itself while it’s operating, so you always have to check the cells. Then, once you find out they’re bad, you must rope them off and tell them not to save anything there anymore. If you buy a 1-terabyte SSD drive, it actually has more than 1 terabyte because it’s grinding itself to death as it operates. For the SSD controllers, that was the initial challenge. But now, storage disk companies have undergone a lot of consolidation. If you look at what’s going on computational storage, we have customers who are doing SSD storage and controllers for the data center that are focused on a particular application, such as video surveillance, so there is computation actually within those controllers that is dealing with that particular use case. That is completely new. Within that computation, you’ll see things like traditional algorithmic, if/then analysis. Then, some of it is trained AI engines. Any of the SSD, enterprise SSD controllers are heading in that direction.”

Topics: SoC NoC network-on-chip enterprise SSD semiconductor engineering arteris ip cache interconnects kurt shuler computational storage AI engines

SemiWiki: SoC Integration - Predictable, Repeatable, Scalable

Bernard Murphy (SemiWiki) gets an update from Kurt Shuler, vice president of Marketing at Arteris IP on the benefits of integrating SoC data and NoC integration. 

SoC Integration - Predictable, Repeatable, Scalable

March 24th, 2021 - Bernard Murphy

On its face System-on-chip (SoC) integration doesn’t seem so hard. You gather and configure all the intellectual properties (IPs) you’re going to need, then stitch them together. Something you could delegate to new college hires, maybe? But it isn’t that simple. What makes SoC integration challenging is that there are so many parts including IPs and connections. Some are moving parts, changing as bugs are fixed. Some, like the interconnect, can only be completely defined when you integrate. There’s a lot of interdependence between these parts. Make a small change like importing a new revision of an IP or adapting to a spec tweak, and the consequences can ripple through your integration, not a big deal, perhaps, early in design. But a very big deal when you’ve finally wrestled hundreds of IPs and tens of thousands of connections into behaving. Then you have to drop in a couple more changes. Surely there’s a better way? Kurt Shuler shares his views on the need.
Topics: SoC NoC network-on-chip semiconductor FlexNoC semiwiki safety XML ip-xact magillem kurt shuler QoS noc interconnect EDA data integration traceability configuration software interface documentation enterprise

EDN: The Network-on-Chip Interconnect is the SoC

Benoit de Lescure, CTO at Arteris IP authors this new series of articles in EDN:

The Network-on-Chip Interconnect is the SoC

March 25th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

“The network is the computer,” coined by John Gage of Sun Microsystems back in 1984, proved incredibly insightful. This idea is re-emerging, this time within the SoC realm. Functions in a chip that communicate with each other—not through simple wires but through complex network elements such as switches, protocol converters, packetizers, and so on—are not so different from the set of computers communicating through a network within a cabinet, or a room, back in 1984.

Topics: SoC NoC AMBA network-on-chip automotive CPU AI arteris ip interconnects QoS DDR ic design EDN bus fabric

Semiconductor Engineering: Domain-Specific Memory

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Domain-Specific Memory

March 11th, 2021 - By Brian Bailey

Rethinking fundamental approaches to memory could have a huge impact on performance.

“Remember video memories — DRAM with built-in shift registers?” asks Michael Frank, fellow and system architect at Arteris IP. “Perhaps GDDR [1-5], special cache tag memories, or associative memories back in the days of TTL? A lot of these have not really survived because their functionality was too specific. They targeted a unique device. You need a large enough domain, and you are fighting against the low cost of today’s DRAM, which has the benefit of high volume and large-scale manufacturing.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip GPUs cache DRAM interconnects Michael Frank HBM

Semiconductor Engineering: Auto OEMs Face New Competitive Threats

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new Semiconductor Engineering article:

Auto OEMs Face New Competitive Threats

March 4th, 2021 - By Ann Steffora Mutschler

EVs are creating openings for non-traditional players, creating havoc in the supply chain.

Indeed, changes in the thinking of automotive OEMs have been evident for at least the past five years, when it was clear that the OEMs intended to start making their own chips — ironically to avoid becoming “the Foxconn of cars,” said Kurt Shuler, vice president of marketing at Arteris IP. “Foxconn does things to spec. But the ideas, the intellectual property, the value-added content reside outside. The ODM lives off of very tiny margins. For the Tier 1s, they’ve always been the specialist in mechanical or hydraulic, traditional automotive electronics, things like that. And now they’re seeing that they’re getting attacked from below from their own suppliers, as the chip guys — Infineon, NXP, and others — start to create reference design systems with their own silicon that can be adopted by a Tier 1. But an OEM also could buy that directly and do their own software. So the Tier 1s also are getting attacked from above by the OEMs.”

Topics: SoC NoC network-on-chip automotive ADAS autonomous driving semiconductor engineering arteris ip interconnects kurt shuler EV Tier 1s ODM

Semiconductor Engineering: Chiplets For The Masses

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Chiplets for The Masses

March 3rd, 2021 - By Brian Bailey

Chiplets are technically and commercially viable, but not yet accessible to the majority of the market. How does the ecosystem get established?

“I look at the pictures of Intel’s new chips, and it turns out there are eight compute tiles that could be called chiplets, put together with some strips in the middle that contain cache and interconnect tiles,” says Michael Frank, fellow and system architect at Arteris IP. “And it is all sitting on a silicon substrate. There are clearly places where it is worth the money, and worth the efforts. But this paradigm has to be built on standards. It needs to cover the electrical properties, communications, physical attributes, etc. You cannot build different chiplets for every company. No matter how you look at it, it is still a chip and you have to go through all the steps you normally would for a tape-out.”

Topics: SoC NoC network-on-chip moore's law semiconductor engineering arteris ip cache interconnects intel Michael Frank chips alliance darpa