Arteris Articles

Semiconductor Engineering: Security Concerns Rise For Connected Autos

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Security Concerns Rise For Connected Autos

April 29th, 2021 - By John Koon

Value of automotive data increases, widening the attack surface.

“We’re seeing a shift in the entire automotive industry, essentially from mechanics to electronics being the core competence of the automotive industry,” said K. Charles Janac, chairman and CEO of Arteris IP. “This includes either influence on architectures or IP design, or maybe even doing entire SoCs, by the car companies and by the Tier 1s, because you need to control your architecture in order to enforce upgradability.”

Topics: SoC NoC network-on-chip ADAS autonomous vehicles semiconductor engineering arteris ip K. Charles Janac interconnects 5G automotive security ISO 21434

SemiWiki: Arteris IP Contributes to Major MPSoC Text

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs.
 
K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.
Topics: SoC NoC ISO 26262 network-on-chip semiconductor AI semiwiki K. Charles Janac kurt shuler noc interconnect cache coherence MPSoC Forum

Semiconductor Engineering: Many Chiplet Challenges Ahead

Michael Frank, fellow and system architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Many Chiplet Challenges Ahead

April 12th, 2021 - By Brian Bailey

Assembling systems from physical IP gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

“The size of the bits and pieces is an issue,” says Michael Frank, fellow and system architect at Arteris IP. “It is perhaps less of an issue with chiplets or 2.5D, where things are mounted on a substrate, but it adds additional challenges for 3D. We are no longer dealing with gravel. It is grains of sand, or even dust specs. It’s more robust to build boards.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects chiplets Michael Frank 5nm ESD

Semiconductor Engineering: More Data Drives Focus On IC Energy Efficiency

Michael Frank, fellow and system architect at Arteris IP are quoted in this new Semiconductor Engineering article:

More Data Drives Focus On IC Energy Efficiency

April 8th, 2021 - By Ann Steffora Mutschler

Decisions that affect how, when, and where data gets processed.

"On the chip side, it’s an engineering discipline. On the other side are the algorithm experts who understand what the masks are and what they want to do,” said Michael Frank, fellow and system architect at Arteris IP.

Topics: SoC NoC network-on-chip machine learning neural networks semiconductor engineering arteris ip interconnects chiplets Michael Frank memory architecture TensorFlow

Semiconductor Engineering: Interconnects In A Domain-Specific World

Kurt Shuler, Vice President of Marketing and Guillaume Boillet, Director of Product Management at Arteris IP are quoted in this new Semiconductor Engineering article:

Interconnects In A Domain-Specific World

April 8th, 2021 - By Brian Bailey

When and where tradeoffs between efficiency and flexibility make sense.

"The prediction of power consumption of chips under a given workload is one of the most complex tasks our industry must tackle today,” says Guillaume Boillet, director of product management for Arteris IP

Kurt Shuler, vice president of marketing at Arteris IP says, “You may have 200 things connected to your NoC at the center of the chip. The NoC tool manages all of the meta data for the IP connected to it. Back-figuring all that information is a huge source of systematic errors. We all make mistakes. And that causes problems, not just for regular chips. But can you imagine that for typical functional safety requirements?”

Topics: SoC NoC functional safety network-on-chip neural networks semiconductor engineering arteris ip interconnects kurt shuler power consumption meta data

Semiconductor Engineering: Privacy Protection A Must For Driver Monitoring

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new Semiconductor Engineering article:

Privacy Protection A Must For Driver Monitoring 

April 1st, 2021 - By Ann Steffora Mutschler

Why driver data collected by in-cabin monitoring systems must be included as part of the overall security system.

Privacy and security has to be addressed at every layer, by all parties, said Kurt Shuler, vice president of marketing at Arteris IP. “We’re getting questions from customers asking, ‘You’ve got this interconnect, it’s a network, you have these firewalls, how do I integrate this into my overall security system for my chip?’ They also want to know how to integrate that in the overall security system of that vehicle subsystem, and how to integrate that into the overall security system for the car, and then the network of cars. If I’m GM, I’ve got a whole network of GM cars running around. Where there’s OnStar, I have to protect that data too, and that’s sitting on servers. The OEM is cognizant of this because they know from market forces that if they screw it up, then people aren’t going to trust them. And even though there are IEEE, ISO, and SAE standards, selling security is like selling insurance. Nobody thinks they need it until after the incident happened. The risk is huge here if you don’t do it right, so you should do everything state of the art. However, there’s nothing currently legally forcing that.”

Topics: SoC NoC functional safety ISO 26262 network-on-chip automotive IEEE semiconductor engineering arteris ip interconnects OEMs security driver monitoring

Semiconductor Engineering: SoC Integration Complexity: Size Doesn't (Always) Matter

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new Semiconductor Engineering article:

SoC Integration Complexity: Size Doesn't (Always) Matter

April 1st, 2021 - By Kurt Shuler

Even small IoT designs can have plenty of complexity in architecture and integration.

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, even using harvested MEMS power instead of a battery, and quick turnaround to build out a huge family of products based on a common SoC platform while keeping tight control on development and unit costs.

Topics: SoC NoC network-on-chip IoT low power semiconductor engineering arteris ip ip-xact interconnects kurt shuler DVFS ip deployment