Arteris Articles

SemiWiki: Architecture Wrinkles in Automotive AI: Unique Needs

Bernard Murphy (SemiWiki) learns from Stefano Lorenzini, Functional Safety Manager at Arteris IP, the difference between AI in automotive and other contexts. 

Architecture Wrinkles in Automotive AI: Unique Needs

May 20th, 2021 - Bernard Murphy

Arteris IP recently spoke at the Spring Linley Processor Conference on April 21, 2021 about Automotive systems-on-chips (SoCs) architecture with artificial intelligence (AI)/machine learning (ML) and Functional Safety. Stefano Lorenzini, Functional Safety Manager at Arteris IP, presented a nice contrast between auto AI SoCs and those designed for datacenters. Never mind the cost or power, in a car we need to provide near real-time performance for sensing, recognition and actuation. For IoT applications we assume AI on a serious budget, power-sipping, running for 10 years on a coin cell battery. But that isn't the whole story. AI in the car is a sort of hybrid, with the added dimension of safety, which makes for unique architecture wrinkles in automotive AI.  
Topics: SoC NoC network-on-chip semiconductor ECC The Linley Group FlexNoC arteris ip semiwiki functional safety manager kurt shuler data centers noc interconnect AI SoCs AI/ML automotive AI Hardware Stefano Lorenzini

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level

EDN: Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

Benoit de Lescure, CTO at Arteris IP authors this 2nd article in a new series for EDN:

Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

May 13th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

In my first article of this series about interconnect design, I explained why on-chip communication has become central to a system-on-chip (SoC) architecture. These architectural decisions determine bandwidth, throughput, quality-of-service (QoS), power usage, safety, and cost. Here, the difference between a world-class achievement and a shortcoming starts with the communication architecture choice.

Topics: ARM NIC-400 SoC NoC network-on-chip automotive mobileye AI arteris ip Benoit de Lescure digital eyeq interconnects communications EDN plug-and-play

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

Semiconductor Engineering: HBM Takes On A Much Bigger Role

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

HBM Takes On A Much Bigger Role

May 13th, 2021 - By Brian Bailey

High-bandwidth memory may be a significant gateway technology that allows the industry to make a controlled transition to true 3D design and assembly.

“The benefit of HBM is really its high bandwidth,” says Michael Frank, fellow and system architect at Arteris IP. “If you have a working data set that fits, it’s fine. To consume that much bandwidth, you are likely to use a decent amount of silicon area to process it. But HBM does not providing the low latency that you get from SRAMs. You have to look at your application. What is your algorithm? In many systems, you sequentially process a lot of data, mostly with the same kind of processing scheme. It’s like SIMD or streaming. Machine learning is typically something like this, where you have large data sets and weights. But HBM is still limited in capacity, and the price is relatively high.”

Topics: SoC NoC network-on-chip machine learning semiconductor engineering arteris ip interconnects Michael Frank DRAMS SMID

Semiconductor Engineering: IC Security Threat Grows As More Devices Are Connected

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

IC Security Threat Grows As More Devices Are Connected 

May 6th, 2021 - By Ann Steffora Mutschler

Awareness increases, but so does the complexity of systems and the potential attack surface.

 “We would expect this industry to be adopting cloud-based software-as-a-service massively, but the reality is different,” said Guillaume Boillet, director of product management at Arteris IP. “The design environment itself is almost always in a customer-owned data center. There has been some push to leverage the benefits of the cloud, and of course it’s very appealing because now you can scale your data centers. But I don’t have an example where, all of a sudden, you’ve got a need for more computing power and you would rather rely on the cloud than build a rack. This is not happening for multiple reasons. One, people are very protective of their IP, of what they’re doing, so it’s been an hindrance for us in terms of support, etc. Also, moving to the SaaS model requires a total rethink of the licensing, because it’s a totally different monetization scheme. I’ve seen examples where this scenario would have required a lot of work and a lot of revamping of the toolset.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects datacenters security Guillaume Boillet ecosystem security

Semiconductor Engineering: NoCs In Authoritative MPSoC Reference

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoCs In Authoritative MPSoC Reference

May 6th, 2021 - By Kurt Shuler

The role of the network-on-chip in ensuring total system safety.

K. Charles Janac, president and CEO of Arteris IP, authored the first chapter in that third section on network-on-chip (NoC) architecture and how it has enabled MPSoCs. 

The chapter starts with the evolution from buses to crossbars to NoCs. Next is a useful overview of a typical approach to architecting and configuring a NoC. As the most configurable intellectual property (IP) in an SoC, getting the design to an optimal solution requires careful planning and refinement. The design evolves, not just the logic but also the topology.

By the way, this book is a technical review, not a marketing pitch. Charlie is quite open that while NoCs share some concepts with “regular” communications networks, the analogy cannot be stretched too far. NoC design is still very much an activity for semiconductor designers, not general network designers.

Topics: SoC NoC functional safety network-on-chip ECC cache coherency IEEE semiconductor engineering arteris ip ASIL D K. Charles Janac interconnects kurt shuler ai accelerators security TMR MPSOC LBIST

Semiconductor Engineering: Steep Spike For Chip Complexity And Unknowns

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Steep Spike For Chip Complexity And Unknowns

May 5th, 2021 - By Ed Sperling

Increased interactions and customizations drive up risk of re-spins or failures.

“There are several aspects that need to be considered, such as making sure the customer is using the right version of the IP,” said K. Charles Janac, chairman and CEO of Arteris IP. “You’re basically enforcing that the IP-XACT parameters are there in order for the IP block to be admitted into the SoC. There’s also the aspect of supply management. Many of these companies have a layout house, a design house, and foundry contractors. If that entire supply chain is IP-XACT — from the interaction between the various parties in the supply chain to what ultimately provide what goes into the SoC — it gets much, much smoother. At the same time, you are going to have some pieces of the chip that are on the leading-edge process and some on the trailing edge, such as analog.

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip K. Charles Janac ip-xact interconnects chiplets inter-chip IPD