Arteris Articles

Semiconductor Engineering: Time For FMEDA Reuse?

Stefano Lorenzini, Fellow & Functional Safety Manager at Arteris IP authored this Semiconductor Engineering article:

Time for FMEDA Reuse?

 July 7th, 2022 - By Stefano Lorenzini

Making it easier to integrate configurable IP into safety-critical systems.

How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA. In fact, an FMEDA does not have to be a table; it could be manifested in scripts or some other form, but a table is the easiest way to think of this information. Think of an FMEDA for an IP, as the concept extends easily to a system-on-chip (SoC). The table has a row for each failure mode that the IP experts can imagine might lead to a critical safety problem. Following identifying information for that failure mode is a description of the effect – the safety problem it might cause. Through fault simulation, the safety engineer determines the likelihood of the root cause problem leading to that effect. If the likelihood is significant, the designer will propose a mitigation technique, such as a parity check to detect the problem or an error-correcting code (ECC) check to correct it. A completed FMEDA then represents a comprehensive safety quality document for that IP, a characterization that an SoC integrator can use when determining the FMEDA for the whole design.

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Topics: IP System-on-Chip functional safety network-on-chip semiconductor engineering SoCs FMEDA scalability traceability Stefano Lorenzini NoCs Arteris IP (AIP)