Arteris IP at DVCon U.S. 2019
Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level
Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"
Abstract: This paper defines the methodology for a composite scoreboarding using Flexible Checker. The Arteris method allows bench test engineers to adapt to ongoing design configuration changes. Flexible Checker provides a solution that is portable across blocks, sub-blocks, and in chip-level environments. The methodology enables flexible transition trace checking, which can define transactions at multiple internal nodes before reaching their endpoints. Flexible Checker is equipped to record vital statistics from end to end, including bandwidth, latency, traffic distribution, count, type, and size in the report phase of the Universal Verification Methodology.
Speaker: Saad Zahid - Arteris IP
Authors: Saad Zahid - Arteris IP
Chandra Veedhi - Arteris IP
Sumit Dhamanwala - Arteris IP
For more information about Arteris IP, download the FlexNoC AI Package datasheet: http://www.arteris.com/download-flexnoc-ai-package-datasheet