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Arteris IP is Hiring a Hardware Verification Engineer in Paris!

Arteris-IP-LinkedIn-1200x628Featured Position!

Hardware Verification Engineer in Paris (Guyancourt), France

Do you want to contribute to the backbone of the some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You'll verify designs created in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll have to ensure that our IPs are matching the specifications before been released to our customers, to be part of a SoC for AI, IoT, automotive, mobile... our IP is used everywhere!

Education Requirements:

• Masters of Science (MS) in engineering, or equivalent 

• Work closely with the digital design team to review and understand specifications, architecture and microarchitecture
• Define, document, develop and execute RTL verification test/coverage  
• Performance verification and power-aware verification and more...

Experience and Qualifications:
• From 1 year to 5 years experience as a Design Verification engineer
• Must have: Knowledge of standard verification flows including simulation and test bench development
• Must have: Knowledge of UVM methodology and System Verilog
• Knowledge of AMBA protocols (AXI) and AMBA VIP is a plus
• Good written and verbal communication skills in both French and English
• Proven ability to work well within a team

For more information on this position and to apply, please click here:

Arteris IP offers a dynamic and challenging work environment for experienced professionals. Our employees receive competitive compensation and benefits, and the ability to be an important part of an increasingly larger global team at Arteris IP. We are on the leading-edge of the System-on-Chip (SoC) movement, and working with some of the world's largest and most technically advanced customers. To view more positions, click here:


Topics: hardware verification arteris ip RTL noc interconnect job SoC designs C/C++ Python