Arteris Ncore has been featured in a detailed article in AnandTech by Andrei Frumusanu titled, "Arteris Announces Ncore Cache-Coherent Interconnect." You can see the big link in the top left of the home page or read it directly at http://anandtech.com/show/10339/arteris-announces-ncore-cachecoherent-interconnect.
This article is significant because it is the most detailed technical "deep-dive" article I've seen on Ncore yet. Andrei has written many articles on embedded systems, SoCs and ARM IP and really understands system architecture.
Here's a top 5 list of my favorite articles by Andrei Frumusanu:
- Arteris Announces Ncore Cache-Coherent Interconnect (of course :-)
- The Samsung Exynos 7420 Deep Dive - Inside A Modern 14nm SoC - almost a year old but one of the best examinations of a complete hardware/software system I have seen. Plus, Arteris FlexNoC is inside!
- The Mobile CPU Core-Count Debate: Analyzing The Real World - near and dear to my heart because Andrei focuses on performance analysis of big.LITTLE SoCs running Linux, and in the process shows that the ARM marketers were on to something special. Brings me back to my days when I was product manager for Intel VTune...
- ARM Announces New CCI-550 and DMC-500 System IPs - yes, ARM CCI is technically competition to the Arteris Ncore cache coherent interconnect, but we're all trying to enable and grow the market for SoC hardware cache coherency. A good discussion of how adding a snoop filter was added to help fix scaling issues with CCI-400.
- HiSilicon Announces New Kirin 950 SoC - Arteris inside! And it shows how Huawei / HiSilicon is taking aggressive steps to create world class mobile phone application processors, both in system architecture and in fast transition to the TSMC 16FF+ process node.
Also, if you want to learn more about cache coherency, download our Ncore technical overview presentation.