Arteris Articles

Madelyn Miller

SemiWiki: An Ah-Ha Moment for Testbench Assembly

by Madelyn Miller, on Tue, Mar 01, 2022 @ 08:00 AM

Bernard Murphy (SemiWiki) gets an update from Arteris IP.

An Ah-Ha Moment for Testbench Assembly

February 28, 2022 - Bernard Murphy

Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing their energy in learning UVM. UVM is fine, so why do we need to talk about anything different? That’s the forest and trees thing. We don’t need to change the way we define testbenches – the behavior and (largely) the top-level structure. But maybe there’s a better way to assemble that top level through a more structured assembly method than through hand-coding or ad-hoc scripting. Still built on UVM at leveraging the standardization benefits of IP-XACT for assembly around VIPs.

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Topics: SoC NoC network-on-chip semiconductor arteris ip semiwiki ip-xact RTL UVM noc interconnect test bench assembly Arteris IP Harmony Trace Paul Graykowski Jama software SoC verification Magillem UTG UVM Testbench Generator Arteris (AIP)

Semiconductor Engineering: Verification Signoff Beyond Coverage

by Madelyn Miller, on Thu, Feb 03, 2022 @ 11:04 AM

Paul Graykowski, Senior Technical Marketing Manager at Arteris IP authored this Semiconductor Engineering article:

Verification Signoff Beyond Coverage

February 3rd, 2022 - By Paul Graykowski

Ensuring implementation and verification match the customer's requirements.

A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. This process iterates until the agreed level of coverage is met. Functional coverage is the metric by which this process is gauged, and it works well within its scope. The major electronic design automation (EDA) vendors have tools to run simulations, accumulate coverage statistics, and help further advance those metrics. But this is not the whole story in signoff.

To learn more about traceability and Arteris Harmony Trace, please download this technical paper: https://www.arteris.com/download-reinventing-traceability-arteris-harmony-trace-paper

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Topics: network-on-chip automotive semiconductor engineering arteris ip verification SoCs compliance EDA traceability NoCs Arteris IP (AIP) validation Arteris Harmony Trace Paul Graykowski

EDN: System Architect: Blueprint of a New Job in Semiconductor Industry

by Madelyn Miller, on Thu, Jan 27, 2022 @ 10:14 AM

Isabelle Geday, VP and GM of IP Deployment at Arteris IP is quoted with EDN's editor-in-chief, Majeed Ahmad in this new article:

System Architect: Blueprint of a New Job in Semiconductor Industry

January 26th, 2022 - By Majeed Ahmad

According to Isabelle Geday, VP and GM of IP deployment at Arteris IP, the job requires a system-oriented mindset, which calls for a holistic approach to ensure the success of the designed systems. “A systems architect needs to have a strong understanding of design and verification and master key aspects for the targeted application and domain.” It also encompasses safety, security and performance, which must be considered at the system level—in the definition of its architecture—to be addressed efficiently.

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Topics: SoC NoC network-on-chip automotive iso26262 arteris ip communications Isabelle Geday EDN Semiconductors defense Arteris IP (AIP) system-on-ships

SemiWiki: Business Considerations in Traceability

by Madelyn Miller, on Wed, Jan 26, 2022 @ 12:28 PM

Bernard Murphy (SemiWiki) gets an update from Arteris IP on why businesses may be increasing pushed to support traceability.

Business Considerations in Traceability

January 26, 2022 - Bernard Murphy

Traceability as an emerging debate around hardware is gaining a lot of traction. As a reminder, traceability is the need to support a disciplined ability to trace from initial OEM requirements down through the value chain to implementation support and confirmed verification in software and hardware. Demand for traceability appears most commonly in safety-critical applications, from automotive and rail to mil-aero. In process industries such as petroleum, petrochemical and pharmaceutical, to power plants and machinery safety-related controls. And that’s just established applications. The more we push the IoT envelope, Industry 4.0, smart cities and homes, the more cannot-fail products we will inevitably create. Safety, reliability, regulations and even simply managing complex and varied requirements from customers have implications for traceability support.

To learn more, click HERE.

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Topics: SoC NoC network-on-chip semiconductor automotive arteris ip semiwiki ip-xact compliance noc interconnect design teams Arteris IP Harmony Trace Paul Graykowski Jama software ISO 14971

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Madelyn Miller

Recent Posts by Madelyn Miller:

SemiWiki: An Ah-Ha Moment for Testbench Assembly

An Ah-Ha Moment for Testbench Assembly

Semiconductor Engineering: Verification Signoff Beyond Coverage

Verification Signoff Beyond Coverage

EDN: System Architect: Blueprint of a New Job in Semiconductor Industry

System Architect: Blueprint of a New Job in Semiconductor Industry

SemiWiki: Business Considerations in Traceability

Business Considerations in Traceability