Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.
Why DRAM memory sharing?
The main motivation for both of these standards is electronic bill of materials (eBoM) cost reduction in mobile phones. The fast 100ns or less round-trip latency of a MIPI LLI or C2C connection is fast enough for the phone’s modem to share the application processor’s RAM and to maintain enough read throughput for cache refills.
This enables the phone manufacturer to remove the modem’s dedicated RAM chip from the phone’s bill of materials (BOM). In addition to saving $2 in BOM cost by removing a 512MB LPDDR2 memory, phone makers free up anywhere from 75 to 100 square millimeters of printed circuit board (PCB) area.
What are the differences between MIPI LLI and C2C?
Although MIPI LLI and C2C have the same business purpose of removing a DRAM from a mobile phone, they differ in their implementations.
MIPI Low Latency Interface (LLI)
MIPI is an open standard managed by the MIPI Alliance. The final 1.0 version of the MIPI LLI specification is expected to be released sometime in late 2011 or early 2012.
MIPI LLI requires only 2 or 4 pins but does require an updated MIPI M-PHY capable of High Speed Gear 2 for mobile phone use models. Round trip latency is less than 80 nanoseconds, and unidirectional throughput is 2.9 Gb/sec using MIPI M-PHY High Speed Gear 2.
Texas Instrument’s upcoming OMAP 5 processor is the only device platform currently announced that will support the future MIPI LLI (it will also support C2C). The number of publicly announced devices with MIPI LLI is expected to increase as the specification is finalized.
C2C has been available since 2010 and is a product containing technology from Texas Instruments and Arteris.
C2C does not require a PHY. However, unlike MIPI LLI’s 2 or 4 pin requirement, C2C requires 28 pins in a mobile phone use model. The interface can be multiplexed with existing DDR pads and is LPDDR I/O compliant.
Round trip latency is 100ns. At 100,000 gates, C2C is very small. It requires 1.2 or 1.8 volts and has unidirectional throughput of 6.4 Gb/sec at 200 MHz DDR speeds and using 16 pins.
Texas Instruments, Intel, Samsung, LG, ST–Ericsson, HiSilicon Technologies, and VIA Telecom have publicly expressed support for and use of C2C.
C2C or MIPI LLI: Which to choose?
The decision between whether to use MIPI LLI or Chip to Chip (C2C) in a chip is dependent upon the interfaces available in the companion chips with which it will connect and the time frame for the product’s release date. Although the trend for chips being developed today is to use C2C, more chips using MIPI LLI are expected to be announced once the final specification is made available. Some chipmakers, such as TI, have chosen to implement both interfaces on their latest applications processors.
With any interface IP, always keep in mind that the companion chips with which you would like to connect may have different connectivity requirements and roadmaps than your own products. Therefore it is important to coordinate with the organizations that create these companion chips, whether these teams are in your company or external.
Learn more about C2C and MIPI LLI interchip link IP:
- Visit the Arteris website C2C product pages
- Read "Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI...oh my!"
- Read "TI OMAP 5 Platform includes MIPI LLI and C2C interchip connectivity"