Arteris Articles

Hogan NoC analysis - Sonics SGN, Arteris FlexNoC, ARM NIC 400: Setting the record straight

arteris samsung qualcomm ti 400Recently, Sonics board member Jim Hogan uploaded some content onto ( that purports to provide unbiased guidance regarding metrics for evaluating network-on-chip technology and interconnect fabrics. I applaud Jim for his analysis of the metrics one should use to evaluate SoC interconnects.

However, in my opinion, his product comparison chart has factual errors with respect to Arteris product capabilities.

Jim Hogan NoC table compares silicon-proven Arteris FlexNoC to unproven Sonics SGN

First, I would like to address an area where the analysis may be confusing or shallow:

In the PPA row of the chart, Jim Hogan compares Sonics SGN’s potential obtainable frequency to his estimates of the frequencies of chips incorporating the silicon-proven Arteris FlexNoC and ARM NIC-400 interconnect fabrics. 

Here are some of the problems with the analysis in this row:

  • Potential performance:  Comparing the potential performance of a technology (“>1 GHz Performance…”) to the actual performance of technologies in shipping chips is a flawed comparison.  There is no relation to the implemented frequencies of SoC interconnect fabrics and the potential frequencies because these speeds are determined by other factors.
    • In most cases, design teams set the interconnect frequency based on a multiple or divisor of the memory controller frequency. (Of course, all these SoCs have multiple clock domains.)
    • There are three main things that impact achievable interconnect frequencies: (1) The amount of logic in the interconnect data flow (for example, advanced QoS or redundancy and safety features, etc.), (2) the number of very long paths within and interconnect that could impact timing closure if not dealt with, and (3) the semiconductor process technology. In the real world, the frequency is a design goal, and the interconnect is adapted to meet it.
    • As an aside, Arteris was marketing >1GHz achievable performance back in 2009 during the FlexNoC Interconnect IP initial product launch.
  • Actual performance:  If one were to compare the interconnect frequencies of actual shipping products, then for Sonics, the speed would have to be measured by a calendar rather than a clock:
    • As far as one can tell from public information, there are no shipping SoC chips designed with Sonics SGN today. So it may be some time before anyone sees a commercial chip using that interconnect to validate the “>1Ghz” performance claim.
    • Also, the current chip with the fastest silicon-proven Arteris FlexNoC fabric runs faster than 533 MHz, so the 533 MHz number in the table is wrong.

Jim Hogan NoC table – with Arteris corrections

I created a separate column in Jim Hogan’s original table (appended below) that summarizes Arteris FlexNoC’s actual features and characteristics, and also added new rows for Latency and Silicon-Proven product adoption. My additions are in blue.

It’s clear that NoC technology is now being adopted by all semiconductor makers creating SoCs with sufficient complexity. And it’s even clearer that Arteris FlexNoC is the gold standard for NoC interconnect fabric IP.

Why have Samsung, Qualcomm, TI and Freescale all adopted Arteris FlexNoC?

But don’t trust my word for it: Ask yourself, “Why have Samsung, Qualcomm, TI and Freescale adopted Arteris FlexNoC as their corporate-standard interconnect fabric IP for their most important chips?”

Innovative technology, excellent engineering, a robust product roadmap and customer satisfaction always speak louder than marketing!




Arteris (Hogan)


Sonics SGN



Performance, Power, Area

>1 GHz Performance, power management signaling and fully clock gated, efficient gate count.

1 Ghz+ capability since initial FlexNoC shipment in 2009 depending on process used. Fastest Customer silicon in production running at 800Mhz in 40nm HP process. Efficient gate and wire count. 0.7mWatt idle power for 1M gate NoC instance.  100s of features for power conservation.

533 MHz, Power Compiler based clock gating, and good area at lower frequencies.


Scalable architecture supports a large number of number of cores (only verification limit). Fabric speed scales for narrow and fast configurations or wide configurations. Architecture supports socket based (AMBA and custom) interfaces separating cores from fabric for flexibility with chip modifications. Existing Interfaces with other fabric IP components for optimal topology configuration.

Unlimited number of IPs. Proven in Customer SoC with over 150 top-level IPs.  Multi-NoC capability. Supports the AMBA protocol portfolio and over 12 other protocols.  Scalable to small designs and blocks as well as large designs.

Flexible multiplexer/de-multiplexer based switches. Modular register slice anywhere in the network. Network interface unit

Quality of Service (QoS)

Initiator-based QoS, with credit-based flow control. Non-blocking.

Distributed QoS. Non-blocking, if you have a blocking architecture you have nothing. Multiple level QoS including Proprietary Pressure Mechanism

Initiator-based QoS.

Virtual Channels

Yes, native virtual channels, with up to 16 channels per link.

For gate count conservation Arteris does not use virtual channels.  Virtual channels are too inefficient and wasteful.


Layout Friendly

Multiple clock schemes supported to allow crossings anywhere in network. Virtual Channels to preserve the architect intent, when modifying network to match layout.

Arteris uses about half the wires of a hybrid bus.  Distributed NoC element architecture eliminates congestion points. Physical aware NoC facilitates consideration of physical constraints during SoC architecture development.

Span distance with pipe point; adds gates and latency.

Power Domain Partitioning

Unlimited number of power and clock domains. Flexible domain crossing can be placed anywhere in the network. Fast hardware controlled domain for power sequencing.

Arteris domain crossings are placed inside the interconnect wherever it is most efficient.

Domain crossing at edge of network.

Memory optimization

Non-blocking fabric enabled by virtual channels combined with credit-based quality of service algorithms. Optional DRAM scheduler can be added to the network.

Optional memory scheduler IP available.

QoS is distributed. Memory interleaver for multi-channel memories. Separate request/ response links make NoC non-blocking by definition.

Initiator-based QoS. Optional memory scheduler IP available.

Cache coherency

ACE-Lite support.

Arteris has full ACE protocol support, in addition to ACE-Lite.  Proven interface to ARM CCI400 coherent interconnect in silicon

ACE-Lite support.

System Verification

Automatic UVM based verification of configured network (includes Synopsys VIP).

Arteris supports industry standard verification methodologies.  Uses Synopsys, Cadence, Mentor and internal VIPs.  Arteris FlexVerifier tool handles unlimited number of switches.

Proprietary verification scheme.



Proprietary Zero Latency NoC capability for latency sensitive connections. Wormhole routing. Fewer gates.  Low latency Network Interface Units (NIUs)




Over 110 designs and 45 tapeouts at 46 customers (as of Sep 2012).  Majority of world’s mobility application processors use Arteris FlexNoC Interconnect. ~100M SoC units shipped in 2012.



Multi-level firewall (superset of TrustZone support).

TrustZone support and customizable security IPs for enhanced security support. TrustZone is a product and trademark of ARM.

Trustzone support.

Chip-Package-Board /Interposer Support

Wide I/O enabled with native fine grained multichannel memory capabilities.

Wide I/O enabled with optional multichannel memory.

Wide I/O enabled with optional multichannel memory.



Topics: Sonics SGN ARM NIC-400 interconnect fabric NoC Arteris FlexNoC