Design News: The Hidden Technology Behind Faster, Smarter Silicon Chips

Unlock the power of artificial intelligence in silicon chip design to generate optimized network-on-chip interconnects while significantly reducing engineering time.

At a Glance

• Advanced AI chips with specialized NoC designs to maximize performance and address complex data needs.
• Machine learning optimizes SoC designs and smart NoCs further improve applications via AI.
• The resulting smart NoC interconnects enhance efficiency by reducing latency and improving bandwidth.

Artificial intelligence (AI) applications, of which machine learning (ML) and deep learning (DL) are subsets, have become ubiquitous. AI functionality is now a common feature in embedded systems, exemplified by autonomous vehicles and robotics.

In many cases, these systems employ special AI-enhanced silicon chips in the form of high-end system-on-chip (SoC) devices. These SoCs, which can comprise tens of billions of transistors, are based on functional units called intellectual property (IP) blocks.

Most IPs, such as processor clusters, memory controllers, and communication functions, will be sourced from trusted third-party vendors. The remaining IPs, such as hardware accelerators that will differentiate this device from competitive offerings, will be developed in-house (Figure 1).

The above diagram provides an extremely basic conceptual overview and is not to scale. The typical number of IPs in one of today’s high-end SoCs ranges from 50 to over 500, while the usual number of transistors in each of these IPs ranges from millions to over a billion.

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