Design & Reuse: Efficient IP Packaging for Today’s SoC Integration

System-on-chip (SoC) design cycles are being reshaped as architectures scale in complexity, driven by AI/ML, high-performance computing, and automotive ADAS. Meeting the compute demands requires managing hundreds of IP blocks, often from multiple internal teams and trusted third-party providers, with absolute consistency from concept through production. Each block brings its own registers, address maps, and bus interfaces. As hardware and software teams increasingly work in parallel, any incomplete or inconsistent data can cause interoperability mismatches, extend debug cycles, and trigger costly late-stage rework.

To avoid these pitfalls, IP descriptions need to be clear. When structured and easy to exchange, they become a single source of truth allowing multi-disciplinary engineering teams to automatically generate error-free RTL netlists, drivers, register models, and verification collateral, keeping everything in sync. It also promotes IP reuse across projects and design derivatives. Additionally, downstream artifacts can now be regenerated, avoiding monotonous hand editing.

Standardizing this process enables a unified methodology for automation. To support this, the industry has embraced IEEE 1685 (IP-XACT), which provides a common, machine-readable IP schema that becomes the shared language between IP metadata and EDA tools, enabling interoperability. The latest version, released in 2022, improves design description accuracy and usability, highlighted below:

• Native SystemVerilog feature support for a more complete and straightforward representation of modern RTL.
• Enhanced connectivity to better capture and manage complex interconnect structures.
• Expanded memory object descriptions for richer representation of system interfaces.
• Better support of parameter propagation, including dependency expression, for more flexible and accurate configuration.

Automating IP-XACT for Accuracy and Efficiency

Arteris Magillem Packaging addresses the practical challenge of producing high-quality IP-XACT descriptions by automatically capturing HDL. It supports both full and incremental packaging, importing Verilog and SystemVerilog from file lists or directories, including mixed-language projects. FileSets are prepared for simulation, synthesis, emulation, and verification.

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