EDN: Network-on-chip (NoC) interconnect topologies explained

Andy Nightingale,  VP Product Management & Marketing at Arteris, authored this EDN article.

July 26th, 2023

Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Functional IP blocks connect to the network-on-chip (NoC) via sockets. In the case of an initiator IP, the socket serializes and packetizes the data generated by the IP, assigns an ID to the packet, and dispatches it into the network. When the packet arrives at its destination IP, the associated socket extracts the data from the packet and transforms it into the protocol required by the IP. A large number of packets can be in flight throughout the network at any given time.

To read the full article on EDN, click here.

Topics: SoC IP System-on-Chip NoC network-on-chip EDN Semiconductors AIP Arteris