EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
- Andy Nightingale
- < 1 min read
Every major semiconductor design shift requires balancing what is possible today with what will be standard tomorrow. As systems-on-chip (SoCs) push past the boundaries of reticle limits, chiplets are an emerging technology that offers a practical path forward. Current chiplet standards provide only a partial framework for today’s multi-die architectures. However, starting designs now delivers practical benefits and allows engineers to influence the standards that will guide the industry for years.
Standards are still under construction
Chiplet standards that define how dies communicate, exchange data reliably, and integrate into larger systems are currently being developed. Despite varying development timelines, the standards are still years from maturity, as their efforts include different levels of scope and complexity. However, the common goal is to create universal standards that allow teams to integrate chiplets from multiple sources without restriction. Three initiatives stand out as the most visible efforts toward standardizing chiplet integration.
A broad coalition of semiconductor leaders backs universal Chiplet Interconnect Express (UCIe). UCIe defines a common physical and protocol layer for die-to-die connectivity and benefits from support from EDA, foundries, and IP companies. UCIe is advancing, with version 1.1 released in 2024, and is expected to reach broad, stable maturity around 2029–2030.
Advanced Interface Bus (AIB), developed by Intel and now under CHIPS Alliance, targets short-reach, low-latency links. While AIB can be considered mature for small niche applications, broader adoption of commercial multi-die packages will not be ready until 2026–2027.
