EE Times article, SoC Interconnect: Don’t DIY!

by Kurt Shuler, On Jun 14, 2019

June 13, 2019 – by Kurt Shuler

The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?

Oh, what a difference IP makes
An example of this comes from an Arteris IP customer. Before this chip company started working with us, they developed only four SoCs per year because it took them more than a month to implement any changes in an interconnect instance created by their internal bus group using their internally developed interconnect IP. Once the customer adopted a commercial interconnect IP, they were able to increase their chip output to over 20 designs per year, which allowed them to economically deliver market segment-tailored chips that captured additional design wins at good gross margins and acceptable prices to customers. What was most interesting to me was that even though the internal team had been creating “optimized” interconnects specifically for the customer for a decade, the new commercial IP solution outperformed theirs in every aspect, and it ultimately saved an average of 3 square millimeters of die area per chip versus the internally-developed interconnect. This savings is about 30 cents per chip, which means many millions of dollars at volume.

For more information, please click here: http://www.arteris.com/resources

Read the entire EETimes DesignLines article, please click here; https://www.eetimes.com/author.asp?section_id=36&doc_id=1334810

SUBSCRIBE TO ARTERIS NEWS