Arteris Articles

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

eetimes_logo_zpsd2838525.pngK. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

What makes for a "good" interconnect?
The interconnect typically makes up about 10% of a finished SoC, yet significantly affects its quality, performance, and delivery schedules. The initial license cost for interconnect IP is relatively small compared to the overall SoC budget, but a “bad” interconnect can cause scheduling, cost, and specification problems. For example, if the interconnect does not allow closing of the timing at the targeted performance, the SoC will not meet frequency specifications — which can cause loss of a design win.

Read the entire EETimes DesignLines article, please click here;

For more Arteris IP information, please click here:  Download peer-reviewed Springer journal paper about Arteris FlexNoC QoS

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation