How Can Network On-Chip IP Can Meet System-On-Chip Demands?

Arteris, an IP supplier, recently developed its FlexGen IP for system-on-chip design. Design News caught up with Rick Bye, Arteris’s Director of Product Management and Marketing, to learn about the product’s function and applications. Rick discusses how network-on-chip IP can help optimize system-on-chip (SoC) design.

DN: What breakthroughs or developments enabled the development of FlexGen? Do machine learning or AI algorithms play a role? 

Rick: FlexGen leverages advancements in AI and machine learning (ML) to automate traditionally time-consuming processes in Network-on-Chip (NoC) design for semiconductor Systems-on-Chip (SoCs). By using ML-based heuristics and algorithms, FlexGen intelligently explores design alternatives and optimizes NoC topologies, resulting in up to 30% wire length reduction and up to 10% lower latency. These innovations are critical for improving power efficiency and achieving superior power, performance, and area (PPA) results. 

DN: How is FlexGen making NoCs an alternative to SoCs or other chip design choices? 

Rick: NoCs are not alternatives to SoCs. NoCs are required to enable successful and efficient interconnect of all the hundreds of different IP blocks that make up today’s SoCs, helping to improve their power, performance and area (PPA). FlexGen allows for multiple SoC architectural design alternatives to be explored in the time to take a manual implementation of a single NoC topology through a traditional flow. 

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