Semiconductor Engineering: Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs

As design complexity increases, manual design approaches can struggle to minimize wire length.

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases latency, elevates power usage, and complicates layout in advanced deep submicron processes where interconnects dominate design constraints. Arteris’ FlexGen smart NoC IP is designed to tackle this challenge by automating NoC generation to minimize wire length while maintaining stringent performance objectives.

Manual design approaches applied to some NoC components struggle to optimize wire length as SoC complexity increases. For instance, an automotive ADAS chip design developed manually by an expert resulted in a total wire length of 313,000 millimeters. Using FlexGen without limits of performance specifications, this figure dropped dramatically to 116,000 millimeters. When performance objectives, such as bandwidth and latency requirements, were applied, FlexGen achieved 280,800 millimeters. As shown in the visual, these results underscore FlexGen’s capability to revolutionize NoC design, providing a measurable edge over traditional methodologies and optimized SoC designs overall.

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