Arteris Articles

Semiconductor Engineering: Chiplets For The Masses

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Chiplets for The Masses

March 3rd, 2021 - By Brian Bailey

semiengineering-logo-2020Chiplets are technically and commercially viable, but not yet accessible to the majority of the market. How does the ecosystem get established?

“I look at the pictures of Intel’s new chips, and it turns out there are eight compute tiles that could be called chiplets, put together with some strips in the middle that contain cache and interconnect tiles,” says Michael Frank, fellow and system architect at Arteris IP. “And it is all sitting on a silicon substrate. There are clearly places where it is worth the money, and worth the efforts. But this paradigm has to be built on standards. It needs to cover the electrical properties, communications, physical attributes, etc. You cannot build different chiplets for every company. No matter how you look at it, it is still a chip and you have to go through all the steps you normally would for a tape-out.”

To read the entire SemiEngineering article, please click here:

Topics: SoC NoC network-on-chip moore's law semiconductor engineering arteris ip cache interconnects intel Michael Frank chips alliance darpa