Semiconductor Engineering: Design Customization Puts Heavy Burden On Verification

Configurability causes an explosion in verification complexity, but the upside is verification engineers are gaining in stature.

Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cadence; Vijay Chobisa, senior director for product management for the Veloce hardware-assisted verification platform at Siemens EDA; and Frank Schirrmeister, executive director for strategic programs for systems solutions at Synopsys. What follows are excerpts of that discussion.

SE: How does chip customization impact verification, especially when it involves multiple chiplets?

Rensch: It’s not pleasant. You infinitely grow the state space whenever you sit there and say, ‘Hey, I want to do this, but I want to change a little bit here, and we want it configurable.’ The state space grows because every marketing guy, when they find out, ‘Oh, you can do X,’ asks, ‘If you do 10% over to the left, can you do Y, Z and A at the same time?’ And they want to change those things. From a verification standpoint, which is my background, it’s awful. It just grows the state space to make the verification much more involved, and it already takes three times as long as a design by making the state space infinite.

Graham: IP providers keep providing all of this customizable IP that grows that space infinitely. Every device revision that has been done forever has been slightly different than the previous one, driven by marketing or some customer requirement, or both. But in the last little while, the thing that’s really been challenging that customers have been challenging me with, at least, is this idea of infinitely configurability, like, ‘We’re going to do nine variants of this thing we’re working on. We’re going to try and do them all in parallel, and they’re all like some parameter difference between them.’ This one’s got 16 widgets, and this one’s got 8 widgets, and something else has got 12, and it’s really the need to do all those in parallel that’s presented the challenge. From a tooling, flow and methodology standpoint, that means that we’re constantly challenged with, how to figure out doing, from the design side, just enough extra. And can I figure out from the verification side, just enough extra so that we can do all those things in parallel with, of course, not nine times the resources? To me, customization has moved in that way where everything has to be parallelized and not quite infinitely configurable or changeable, but not far away.

To read the full article on SemiEngineering, click here.