Arteris Articles

Semiconductor Engineering: Many Chiplet Challenges Ahead

Michael Frank, fellow and system architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Many Chiplet Challenges Ahead

April 12th, 2021 - By Brian Bailey

semiengineering-logo-2020Assembling systems from physical IP gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

“The size of the bits and pieces is an issue,” says Michael Frank, fellow and system architect at Arteris IP. “It is perhaps less of an issue with chiplets or 2.5D, where things are mounted on a substrate, but it adds additional challenges for 3D. We are no longer dealing with gravel. It is grains of sand, or even dust specs. It’s more robust to build boards.”

To read the entire SemiEngineering article, please click here:

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects chiplets Michael Frank 5nm ESD