Arteris Articles

Semiconductor Engineering: Power Optimization: What's Next?

Guillaume Boillet, Director of Product Management at Arteris IP is quoted in this new article in Semiconductor Engineering:

Power Optimization: What's Next!

May 17th, 2021 - By Brian Bailey

semiengineering-logo-2020Clock gating and power gating were a good start, but there is much more that can and should be done to minimize power.

“The efforts in terms of methodology, compute resources and engineering talent to deploy system-level techniques are definitely non-negligible,” says Guillaume Boillet, director of product management for Arteris IP. “Only the most advanced and power-savvy design teams invest in those.”

To read the entire SemiEngineering article, please click here: https://semiengineering.com/power-optimization-whats-next/

Topics: SoC NoC network-on-chip dynamic power machine learning semiconductor engineering arteris ip interconnects RTL Guillaume Boillet clock-gating macro-level