Arteris Articles

Semiconductor Engineering: Von Neumann Is Struggling

Michael Frank, Fellow and System Architect at Arteris IP is quoted in today's Semiconductor Engineering blog:

Von Neumann Is Struggling

January 18th, 2021 - By Brian Bailey

The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architecture.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

Topics: SoC Interconnect NoC network-on-chip memory CPU neural networks semiconductor engineering accelerators chip architectures

Semiconductor Engineering: Get Ready For Dynamic Extensibility

Kurt Shuler, vice president of marketing at Arteris IP comments in this new  Semiconductor Engineering article:

Data Strategy Shifting Again In Cars

June 8th, 2020 - By Brian Bailey

How late can something be deferred during the development process? With dynamically extensible processors, that may be while it's operating.  
This places additional burdens on the algorithms. “They need something that’s much more specific for the problem they’re trying to solve, such as near real-time vision, while probably mixing that with other sensors like LiDAR and radar,” says Kurt Shuler, vice president of marketing at Arteris IP. “It’s not as general-purpose as something that you’d see from the more academic benchmark. So those guys are having to innovate a lot more than the traditional AI algorithms that you read about.”
Topics: SoC automotive ADAS NoC technology semiconductor engineering safety LIDAR kurt shuler accelerators noc interconnect IP market data flow management

Arteris IP Presents: Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip

This presentation titled, "Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip," presented by Kurt Shuler, VP of Marketing and Functional Safety Manager (FSM) at Arteris IP, and Diego Botero, Functional Safety Engineer at Arteris IP, to an audience at the ISO 26262 for Semiconductors (Munich) Conference.

Topics: functional safety ISO 26262 Systems-on-Chip FlexNoC kurt shuler accelerators ML/AI automotive chips IQPC

SemiWiki: Why High-End ML Hardware Goes Custom

Kurt Shuler, VP Marketing at Arteris IP,  provides more insight into what's happening in this highly dynamic space in the latest SemiWiki blog written by Bernard Murphy (SemiWiki):

Why High-End ML Hardware Goes Custom

January 30th, 2019 - By Bernard Murphy

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.

 For more information, download this FlexNoC AI Package datasheet;

Topics: NoC semiconductor semiwiki kurt shuler AI chips flexnoc ai package accelerators noc interconnect ML-centric design