Arteris Articles

Semiconductor Engineering: The High But Often Unnecessary Cost Of Coherence

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new with Semiconductor Engineering article:

The High But Often Unnecessary Cost Of Coherence

December 22nd, 2021 - By Brian Bailey

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?


“Coherence is a contract between agents that says, ‘I promise you that I will always provide the latest data to you,'” says Michael Frank, fellow and system architect at Arteris IP. “It is mostly important when you have a lot of people sharing the same data set. Coherence between equal peers is very important and will not go away.”

Topics: network-on-chip FPGAs cache coherency artificial intelligence semiconductor engineering arteris ip bandwidth CPUs SoCs accelerators dataflow NoCs Arteris IP (AIP) on-chip cache

Semiconductor Engineering: What Is An XPU?

Michael Frank, Fellow and System Architect at Arteris IP is quoted throughout this new article in Semiconductor Engineering:

What Is An XPU? 

November 11th, 2021 - By Brian Bailey

Almost every letter of the alphabet has been used to describe a processor architecture, but under the hood they all look very similar.


“Most of these things are not really a processor in the sense of being a CPU,” says Michael Frank, fellow and system architect at Arteris IP. “They’re more like a GPU, an accelerator for a special workload, and there is quite a bit of diversity within them. Machine learning is a class of processors, and you just call them all machine learning accelerators, yet there is a large variety of the part of the processing they accelerate.”


Topics: network-on-chip GPU semiconductor engineering arteris ip CPUs SoCs accelerators DSP Michael Frank NoCs Arteris IP (AIP)

Semiconductor Engineering: Von Neumann Is Struggling

Michael Frank, Fellow and System Architect at Arteris IP is quoted in today's Semiconductor Engineering blog:

Von Neumann Is Struggling

January 18th, 2021 - By Brian Bailey

The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architecture.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

Topics: SoC Interconnect NoC network-on-chip memory CPU neural networks semiconductor engineering accelerators chip architectures

Semiconductor Engineering: Get Ready For Dynamic Extensibility

Kurt Shuler, vice president of marketing at Arteris IP comments in this new  Semiconductor Engineering article:

Data Strategy Shifting Again In Cars

June 8th, 2020 - By Brian Bailey

How late can something be deferred during the development process? With dynamically extensible processors, that may be while it's operating.  
 
This places additional burdens on the algorithms. “They need something that’s much more specific for the problem they’re trying to solve, such as near real-time vision, while probably mixing that with other sensors like LiDAR and radar,” says Kurt Shuler, vice president of marketing at Arteris IP. “It’s not as general-purpose as something that you’d see from the more academic benchmark. So those guys are having to innovate a lot more than the traditional AI algorithms that you read about.”
 
Topics: SoC automotive ADAS NoC technology semiconductor engineering safety LIDAR kurt shuler accelerators noc interconnect IP market data flow management