Arteris Articles

EDN: Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

Benoit de Lescure, CTO at Arteris IP authors this 2nd article in a new series for EDN:

Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

May 13th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

In my first article of this series about interconnect design, I explained why on-chip communication has become central to a system-on-chip (SoC) architecture. These architectural decisions determine bandwidth, throughput, quality-of-service (QoS), power usage, safety, and cost. Here, the difference between a world-class achievement and a shortcoming starts with the communication architecture choice.

Topics: ARM NIC-400 SoC NoC network-on-chip automotive mobileye AI arteris ip Benoit de Lescure digital eyeq interconnects communications EDN plug-and-play

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

SemiWiki: Arteris IP Contributes to Major MPSoC Text

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs.
 
K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.
Topics: SoC NoC ISO 26262 network-on-chip semiconductor AI semiwiki K. Charles Janac kurt shuler noc interconnect cache coherence MPSoC Forum

EDN: The Network-on-Chip Interconnect is the SoC

Benoit de Lescure, CTO at Arteris IP authors this new series of articles in EDN:

The Network-on-Chip Interconnect is the SoC

March 25th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

“The network is the computer,” coined by John Gage of Sun Microsystems back in 1984, proved incredibly insightful. This idea is re-emerging, this time within the SoC realm. Functions in a chip that communicate with each other—not through simple wires but through complex network elements such as switches, protocol converters, packetizers, and so on—are not so different from the set of computers communicating through a network within a cabinet, or a room, back in 1984.

Topics: SoC NoC AMBA network-on-chip automotive CPU AI arteris ip interconnects QoS DDR ic design EDN bus fabric