Arteris Articles

Electronic Design Article: Making ISO 26262 Traceability Practical


This Electronic Design article, 'Making ISO 26262 Traceability Practical', covers Arteris IP's Harmony Trace in this piece authored by Paul Graykowski, Senior Technical Marketing Manager. 

March 4 , 2021 - By Paul Graykowski

The ISO 26262 standard states that functional-safety assessors should consider if requirements management, including bidirectional traceability, is adequately implemented. The standard doesn’t specify how an assessor should go about accomplishing this task. However, it’s reasonable to assume that a limited subset of connections between requirements and implementation probably doesn’t rise to the expectation.

 

For more information about Arteris Harmony Trace please visit: https://www.arteris.com/harmony-trace-design-data-intelligence

 

Topics: NoC functional safety ISO 26262 network-on-chip autonomous vehicles ip-xact SoCs AI chips EDA electronic design traceability Arteris IP (AIP) Arteris Harmony Trace Paul Graykowski HSI PLM ALM

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

Semiconductor Engineering: Software-Defined Vehicles

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Software-Defined Vehicles

September 4th, 2020 - By Bryon Moyer

The electrification of cars makes all sorts of things possible. 

“There’s a big open question regarding how these updates affect functional safety,” said Kurt Shuler, vice president of marketing at Arteris IP . “Is it practical to completely redo the safety analysis for each update?”
 
Topics: SoC NoC functional safety ISO 26262 automotive ADAS NoC technology semiconductor engineering soc architecture kurt shuler AI chips noc interconnect IP market

Semiconductor Engineering: Interconnects Emerge As Key Concern For Performance

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Interconnects Emerge As Key Concern For Performance

September 3rd, 2020 - By Ed Sperling

Complexity, abundant options, and limits on tooling make this an increasingly challenging area. 

“On the AI side of things, the architecture is being determined by the capabilities of the interconnect,” said Kurt Shuler, vice president of marketing at Arteris IP . “It’s not just about the individual processing elements. It’s how do you get data between the processing elements and a whole bunch of local memories. In a lot of these AI chips, for power as well as latency and bandwidth, they want to limit as much as possible going off to DRAM, which means you’ve got to do the processing in situ within the chip. You can think of the interconnect as knobs and dials of what you’re capable of doing within these huge AI chips.”
 
Topics: SoC NoC NoC technology semiconductor engineering soc architecture DRAM AI chips noc interconnect IP market