Arteris Articles

EE Times article, AI Startups Plateau, AI SoCs Soar, and the Edge Diverges

Laurent Moll, Chief Operating Officer at Arteris IP, sits down with Junko Yoshida in this new EE Times article.

May 13th, 2021 - by Junko Yoshida

Laurent Moll, chief operating officer at Arteris, predicts that in the future, “everyone has some kind of AI in their SoCs.” That is good news for Arteris, because its business is in helping companies (large and small, or new and old) integrate SoCs by providing network-on-chip (NoC) IP and IP development tools.

Topics: semiconductor ADAS eetimes AI SoCs AI chips data centers noc interconnect smartphones SoC IP hyperscalers googles TPU car OEMS edge ai

Semiconductor Engineering: Software-Defined Vehicles

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Software-Defined Vehicles

September 4th, 2020 - By Bryon Moyer

The electrification of cars makes all sorts of things possible. 

“There’s a big open question regarding how these updates affect functional safety,” said Kurt Shuler, vice president of marketing at Arteris IP . “Is it practical to completely redo the safety analysis for each update?”
 
Topics: SoC NoC functional safety ISO 26262 automotive ADAS NoC technology semiconductor engineering soc architecture kurt shuler AI chips noc interconnect IP market

Semiconductor Engineering: Interconnects Emerge As Key Concern For Performance

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Interconnects Emerge As Key Concern For Performance

September 3rd, 2020 - By Ed Sperling

Complexity, abundant options, and limits on tooling make this an increasingly challenging area. 

“On the AI side of things, the architecture is being determined by the capabilities of the interconnect,” said Kurt Shuler, vice president of marketing at Arteris IP . “It’s not just about the individual processing elements. It’s how do you get data between the processing elements and a whole bunch of local memories. In a lot of these AI chips, for power as well as latency and bandwidth, they want to limit as much as possible going off to DRAM, which means you’ve got to do the processing in situ within the chip. You can think of the interconnect as knobs and dials of what you’re capable of doing within these huge AI chips.”
 
Topics: SoC NoC NoC technology semiconductor engineering soc architecture DRAM AI chips noc interconnect IP market

Semiconductor Engineering: Variables Complicate Safety-Critical Device Verification

Kurt Shuler, Vice President of Marketing at Arteris IP participates in this new "Experts at the Table" article in Semiconductor Engineering:

Variables Complicate Safety-Critical Device Verification 

July 1st, 2020 - By Ann Steffora Mutschler

What's the best way to approach designs like AI chips for automotive that can stand the test of time? 

 
SE: Where does the industry stand with the task of verifying safety-critical devices today?
 
Kurt Shuler responds, "At the chip level we still have a situation where the verification people and methodologies are separate from the functional safety people and methodologies. This results in some overlap and rework. As tools and data interchange standards (like IEEE P2851 being led by both IEEE and Accellera) mature, we’ll be able to have more automation where functional safety validation through fault injection can be executed as part of regular verification processes. This will help everyone in the industry have more confidence that products don’t regress in diagnostic coverage as new versions are developed and will provide integrators/users of safety-critical systems to more easily perform fault injection validation of safety mechanisms if they desire."
 
Topics: SoC ISO 26262 automotive NoC technology semiconductor engineering ASIL D AI chips noc interconnect IP market IEEE P2851 fault injection