by Madelyn Miller, on Mon, Sep 17, 2018 @ 07:54 PM
Holger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.
News and original writing about on-chip interconnects, on-chip communications and the semiconductor intellectual property ("semi IP") industry.
Arteris IP HQ
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+33 1 61 37 38 40
Arteris IP Korea
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Seoul 13494 KOREA
+82 (70) 4849-2867
Contact: Rich Yeon, rich.yeon@arteris.com
+82 (10) 4704 9526
Arteris IP Austin
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Austin, TX 78729 USA
Arteris IP Greater China
Room 2708, Yunfeng Mansion,
No.8. Zhongshan North Road, Nanjing,
JiangSu Province, China
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Contact: greater.china@arteris.com
+86 25 58355692
Arteris Semiconductor Technology (Nanjing) Co., Ltd
Room 310, Zhixin Technology Building (Chuangxin Incubator), 15 Xinghuo Road
JiangBei New District
Nanjing, China, 210038
安通思半导体技术（南京）有限公司
江苏省南京市江北新区星火路15号智芯科技大厦综合楼（创芯孵化器）310室
邮编：210038
Contact: greater.china@arteris.com
+86 25 58355692
Arteris IP KK (Japan)
#402, 2-10-15 Shibuya, Shibuya-ku
Tokyo JAPAN 150-0002
Contact: japan_sales@arteris.com
+81 3 4405 0399
