by Madelyn Miller, on Mon, Sep 17, 2018 @ 05:54 PM
Holger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.
News and original writing about on-chip interconnects, on-chip communications and the semiconductor intellectual property ("semi IP") industry.
Arteris IP HQ
595 Millich Dr Suite 200
Campbell, CA 95008 USA
+1 408 470 7300
Arteris IP Austin
9601 Amberglen Blvd, Suite 117
Austin, TX 78729 USA
Arteris IP Korea
U-Space 2B, #1001,
670, Daewangpangyo-ro Bundang-gu,
Seongnam-si, Gyeonggi-do,
Seoul 13494 KOREA
+82 (70) 4849-2867
Contact: Rich Yeon, rich.yeon@arteris.com
+82 (10) 4704 9526
Arteris S.A.S (France)
Immeuble le Cristal
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78280 Guyancourt Cedex – FRANCE
+33 1 61 37 38 40
Arteris IP Greater China
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上海市长宁区长宁路1193号来福士广场T3, 2278室 邮编：200051
Contact: greater.china@arteris.com
+86 137 6141 2028
Arteris KK (Japan)
Nisso 16th building, 3-8-8, Shinyokohama,
Kohoku-ku, Yokohama City
Kanagawa, JAPAN 222-00333
Contact: japan_sales@arteris.com
+81 45-473-5511
