Arteris Articles

Arteris IP Has a New Updated Website!

Arteris IP has a new website!

Topics: SoC NoC ArterisIP noc interconnect ML/AI IP market SoC IP chip design ip deployment

Semiconductor Engineering: New Design Approaches For Automotive

Kurt Shuler, VP of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

New Design Approaches For Automotive

July 1st, 2021 - By Ann Steffora Mutschler

OEMs steer toward executable specs using model-based systems engineering.


“If you’re creating an anti-lock braking system or a windshield washer or something like that, it’s relatively simple and you don’t have to spend much time with these tools to be able to come up with that model,” said Kurt Shuler, vice president of marketing at Arteris IP. “But once you get to something really complex like a system on chip — just like with creating SystemC models or the like — you could spend more time than you would on the RTL, or on writing the specs for the RTL, the requirements and use cases for the specs for the RTL, or a SysML model.”

Topics: SoC NoC ISO 26262 ArterisIP SystemC semiconductor engineering arteris ip RTL kurt shuler SoC assembly SysML MBSE

Semiconductor Engineering: IP-XACT Is Back, For All The Right Reasons

Vincent Thibaut, Director of IP Deployment Product Strategy at Arteris IP authored this new article in Semiconductor Engineering:

IP-XACT Is Back, For All The Right Reasons

July 1st, 2021 - By Vincent Thibaut

Providing collaborating teams a single and reliable source of truth for the design.

The intent behind IP-XACT has always been to provide a bridge between system-on-chip (SoC) assembly and larger considerations. This standard has additionally been used to adapt to multi-sourced and constantly evolving intellectual property (IP) that design and product teams build, often in different companies. Moreover, it was used to interface with product development beyond the specialized needs of logic design. Admittedly, it was developed early, offering a solution to a problem not yet widely recognized. It was early, but it was not wrong. Market changes are pushing more and more SoC builders in this direction in mature and emerging semiconductor and systems companies. Production needs are finally catching up with this standard.

Topics: SoC ArterisIP semiconductor engineering arteris ip ip-xact SoC assembly Tier 1s IP Deployment Division traceability hyperscalers APIs IP licenses cloud compute resources compute farm resources

SemiWiki: That Last Level Cache is Pretty Important

Bernard Murphy talked to Kurt Shuler to get an update on the Arteris IP CodaCache IP. That led to some insights not just on what has changed but also why last level cache is so important in this new SemiWiki blog:

That Last Level Cache is Pretty Important

April 21st, 2020 - By Bernard Murphy

Last-level cache seemed to me like one of those, yeah I get it, but sort of obscure technical corners that only uber-geek cache specialists would care about. Then I stumbled on an AnandTech review on the iPhone 11 Pro and Max and started to understand that this contributes to more than just engineering satisfaction.

For more information, please download this paper: https://www.arteris.com/download-technical-paper-codacache-helping-to-break-the-memory-wall

Topics: SoC ISO 26262 semiconductor ArterisIP AI semiwiki last level cache kurt shuler noc interconnect memory hierarchy Coda Cache LLC