Arteris Articles

Semiconductor Engineering: The Role Of NoCs In System-Level Services

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

The Role Of NoCs In System-Level Services

September 8th, 2020 - By Kurt Shuler

The central nervous system of SoCs is expanding to help manage things like QoS and performance.

The primary objective of any network-on-chip (NoC) interconnect is to move data around a chip as efficiently as possible with as little impact as possible on design closure while meeting or exceeding key design metrics (PPA, etc.). These networks have become the central nervous system of SoCs and are starting to play a larger role in system-level services like quality of service (QoS), debug, performance analysis, safety and security because these on-chip interconnects transport and “see” most if not all of the of the on-chip dataflow. Think of the NoC as the SoC’s “all seeing eye” and you’ll have a better understanding of what is technically possible.
 
Topics: SoC NoC ISO 26262 SoC QoS automotive semiconductor engineering soc architecture ASIL D kurt shuler QoS noc interconnect IP market

Semiconductor Engineering: Virtualization In The Car

Stefano Lorenzini, Functional Safety Manager at Arteris IP is quoted in this new article in Semiconductor Engineering:

Virtualization In The Car

August 6th, 2020 - By Ann Steffora Mutschler

How and why abstraction layers are becoming essential in automotive design.

 
“It’s a way to create multiple virtual instantiations of the same hardware, and every instance is virtually dedicated to a specific product or software or application,” said Stefano Lorenzini, functional safety manager at Arteris IP . “The hypervisor is a bare-metal operating system that runs directly on the hardware and creates an intermediate layer with respect to other application or software programs that are running on top. So if you want to look to the architecture from the top to the bottom, you see the application, then you see the hypervisor, and then you see the hardware layer. The hypervisor is the thing that creates this illusion to the application that every resource of the SoC is dedicated to them.”
 
Topics: SoC automotive autonomous vehicles NoC technology semiconductor engineering soc architecture AI ASIL D functional safety manager noc interconnect IP market automotive electronics

Semiconductor Engineering: Variables Complicate Safety-Critical Device Verification

Kurt Shuler, Vice President of Marketing at Arteris IP participates in this new "Experts at the Table" article in Semiconductor Engineering:

Variables Complicate Safety-Critical Device Verification 

July 1st, 2020 - By Ann Steffora Mutschler

What's the best way to approach designs like AI chips for automotive that can stand the test of time? 

 
SE: Where does the industry stand with the task of verifying safety-critical devices today?
 
Kurt Shuler responds, "At the chip level we still have a situation where the verification people and methodologies are separate from the functional safety people and methodologies. This results in some overlap and rework. As tools and data interchange standards (like IEEE P2851 being led by both IEEE and Accellera) mature, we’ll be able to have more automation where functional safety validation through fault injection can be executed as part of regular verification processes. This will help everyone in the industry have more confidence that products don’t regress in diagnostic coverage as new versions are developed and will provide integrators/users of safety-critical systems to more easily perform fault injection validation of safety mechanisms if they desire."
 
Topics: SoC ISO 26262 automotive NoC technology semiconductor engineering ASIL D AI chips noc interconnect IP market IEEE P2851 fault injection

SemiWiki: AI, Safety and Low Power, Compounding Complexity

Bernard Murphy talked to Kurt Shuler about the complexities of combining low power, safety and AI constraints in a design. Design challenges have evolved beyond PPA to encompass new constraints but these are still manageable, with the right architecture in this new SemiWiki blog:

AI, Safety and Low Power, Compounding Complexity 

April 28th, 2020 - By Bernard Murphy

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.

 

Topics: SoC ISO 26262 semiconductor Toshiba ADAS Ncore FlexNoC AI semiwiki ASIL D noc interconnect memory hierarchy