Arteris Articles

Semiconductor Engineering: Data Explosion Pushes Boundaries of IC Interconnects

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Data Explosion Pushes Boundaries of IC Interconnects

September 22nd, 2021 - By Ann Steffora Mutschler

Design teams rethink the movement of data on-chip, off-chip, and between chips in a package.


“As chips become extremely large, the interconnect is touching all of the IP blocks in the chip. Benoit de Lescure, CTO at Arteris IP. “In this way, the interconnect is growing like the chip. Other components are not. A PCI controller will stay a PCI controller, but the interconnect size grows along with the size of the chip ,so there are scalability issues, especially because designing a good interconnect requires an understanding of how it will be implemented physically. How will it connect all those components on the chip? What amount of free space on the die will be left for the interconnect to use? What switch topology are you going to implement so that the physical aspects are easier later on? As the size of the problem grows bigger, it becomes significantly more difficult to come up with good interconnect decisions.”

Topics: Interconnect autonomous driving semiconductor engineering arteris ip Benoit de Lescure SoCs kurt shuler PHY scalability floorplan PCI controller switch topology D2D digital controller

EDN: How NoCs Ace Power Management and Functional Safety in SoCs

Benoit de Lescure, CTO at Arteris IP authors this 3rd article in a new series for EDN:

How NoCs Ace Power Management and Functional Safety in SoCs

September 15th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

This third article highlights how NoC technology provides capabilities like power management and functional safety that are not possible with older crossbar-based interconnect technologies. For design teams creating modern SoCs, whether large datacenter AI accelerators or power-sipping IoT sensors, NoC interconnect technology is key to implementing these SoC architectures and optimizing the dataflow within them.

To catch up on the first and second articles in this series, click below:

Topics: ARM NIC-400 SoC NoC functional safety network-on-chip crossbar automotive AI arteris ip Benoit de Lescure interconnects EDN LBIST Design Management Power Management Semiconductors DVSF

EDN: Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

Benoit de Lescure, CTO at Arteris IP authors this 2nd article in a new series for EDN:

Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

May 13th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

In my first article of this series about interconnect design, I explained why on-chip communication has become central to a system-on-chip (SoC) architecture. These architectural decisions determine bandwidth, throughput, quality-of-service (QoS), power usage, safety, and cost. Here, the difference between a world-class achievement and a shortcoming starts with the communication architecture choice.

Topics: ARM NIC-400 SoC NoC network-on-chip automotive mobileye AI arteris ip Benoit de Lescure digital eyeq interconnects communications EDN plug-and-play

Semiconductor Engineering: Firmware Skills Shortage

Benoit de Lescure, CTO at Arteris IP is quoted in this new Semiconductor Engineering article:

Firmware Skills Shortage

February 25th, 2021 - By Brian Bailey

Adding intelligence into devices requires a different skill set, and finding enough qualified people is becoming a challenge — especially in less glamorous areas.

“I was working in the image compression domain 20 years ago,” says Benoit de Lescure, CTO for Arteris IP. “We had a similar issue, both with off-the-shelf DSP, and our own specialized DSP. Finding people to make efficient use of the SIMD hardware was extremely difficult, because you need to ‘think parallel’. But few people are ready to deep-dive into a hardware architecture that might be obsolete two or three years from now.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip Benoit de Lescure DSP SIMD