Arteris Articles

Semiconductor Engineering: What Happened To Execute-In-Place?

Michael Frank, Fellow and Chief Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

What Happened To Execute-In-Place?

August 25th, 2020 - By Bryon Moyer

The concept as it was originally conceived no longer applies. Here’s why.

“Demand-paging virtual memory is nothing else than a cache,” noted Michael Frank, fellow and chief architect at Arteris IP . But then Android came available for free, unlike the planned OSes. So the strategy changed from one of demand-paging to moving the entire code base from flash to DRAM, and then using the SRAM cache mechanism to further manage instruction access times — all in the interest of lower cost.
Frank also stated, “My definition of execute in place is where you do not have an address change, where you execute in a cached way, and your original source of the code or the data is still at the same address that you are executing at.”
Topics: SoC NoC technology semiconductor engineering soc architecture AI cache DRAM noc interconnect IP market SRAM MCUs

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC cache coherent IP CPU Ncore semiwiki cache CodaCache on-chip memory performance multi-processor systems congestion configurability last level cache scratchpad way partitioning

Semiconductor Engineering: Power Optimization Strategies Widen

Benoit de Lescure, Sr. Director of Technology at Arteris IP, quoted in this Semiconductor Engineering article:

Power Optimization Strategies Widen


May 10th, 2018 - By Brian Bailey

Topics: low power semiconductor engineering arteris ip cache car external memory ADAS systems complex doc