Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design.
Arteris IP Contributes to Major MPSoC Text
April 29th, 2021 - Bernard Murphy
by Madelyn Miller, on Wed, Apr 28, 2021 @ 12:48 PM
Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design.
April 29th, 2021 - Bernard Murphy
by Madelyn Miller, on Tue, Mar 03, 2020 @ 12:34 PM
Kurt Shuler, VP of Marketing at Arteris IP updates Bernard Murphy (SemiWiki) on how trends in AI and safety are changing the design considerations for smart features in our cars in this new blog:
February 3rd, 2020 - By Bernard Murphy
The potential for AI in cars, whether for driver assistance or full autonomy, has been trumpeted everywhere and continues to grow. Within the car we have vision, radar and ultrasonic sensors to detect obstacles in front, behind and to the side of the car. Outside the car, V2x promises to share real-time information between vehicles and other sources so we can see ahead of vehicles in front of us, around corners to detect hazards, and see congested traffic and emergency vehicles. Also this AI can improve on the fly, adapting to new conditions through training updates from the cloud.
by Madelyn Miller, on Thu, Aug 01, 2019 @ 12:58 PM
Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:
August 1st, 2019 - By Ann Steffora Mutschler
Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...
Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.
“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”
For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet
by Madelyn Miller, on Fri, Apr 19, 2019 @ 06:00 AM
Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:
March 13th, 2019 - By Bernard Murphy
How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.
No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.
News and original writing about on-chip interconnects, on-chip communications and the semiconductor intellectual property ("semi IP") industry.
Arteris IP HQ
595 Millich Dr Suite 200
Campbell, CA 95008 USA
+1 408 470 7300
Arteris IP Deployment
251, rue du Faubourg Saint-Martin
75010 Paris, France
+33 1 40 21 35 50
Arteris IP SAS (France)
2 rue George Stephenson
78180 Montigny le Bretonneux - France
+33 1 61 37 38 40
Arteris IP Korea
U-Space 2B, #1001,
670, Daewangpangyo-ro Bundang-gu,
Seongnam-si, Gyeonggi-do,
Seoul 13494 KOREA
+82 (70) 4849-2867
Contact: Rich Yeon, rich.yeon@arteris.com
+82 (10) 4704 9526
Arteris IP Austin
9601 Amberglen Blvd, Suite 117
Austin, TX 78729 USA
Arteris IP Greater China
Room 2708, Yunfeng Mansion,
No.8. Zhongshan North Road, Nanjing,
JiangSu Province, China
中国江苏省南京市中山北路8号云峰大厦2708室
Contact: greater.china@arteris.com
+86 25 58355692
Arteris Semiconductor Technology (Nanjing) Co., Ltd
Room 310, Zhixin Technology Building (Chuangxin Incubator), 15 Xinghuo Road
JiangBei New District
Nanjing, China, 210038
安通思半导体技术(南京)有限公司
江苏省南京市江北新区星火路15号智芯科技大厦综合楼(创芯孵化器)310室
邮编:210038
Contact: greater.china@arteris.com
+86 25 58355692
Arteris IP KK (Japan)
#402, 2-10-15 Shibuya, Shibuya-ku
Tokyo JAPAN 150-0002
Contact: japan_sales@arteris.com
+81 3 4405 0399