Arteris Articles

SemiWiki: Arteris IP Contributes to Major MPSoC Text

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

You might have heard of the Multicore and Multiprocessor SoC (MPSoC) Forum sponsored by IEEE and other industry associations and companies. This group of top-notch academic and industry technical leaders gets together once a year to talk about hardware and software architecture and applications for multicore and multiprocessor systems-on-chip (SoCs). They gather to debate the latest and greatest ideas to meet emerging needs.
 
K. Charles Janac, president and CEO of Arteris IP, wrote the first chapter in the third section on network-on-chip (NoC) architectures. I’m impressed that what must be considered a definitive technical reference on MPSoCs required a chapter on NoC interconnect, and the editors turned to Arteris IP to write that chapter.
Topics: SoC NoC ISO 26262 network-on-chip semiconductor AI semiwiki K. Charles Janac kurt shuler noc interconnect cache coherence MPSoC Forum

SemiWiki: Trends in AI and Safety for Cars

Kurt Shuler, VP of Marketing at Arteris IP updates Bernard Murphy (SemiWiki) on how trends in AI and safety are changing the design considerations for smart features in our cars in this new blog:

Trends in AI and Safety for Cars

February 3rd, 2020 - By Bernard Murphy

The potential for AI in cars, whether for driver assistance or full autonomy, has been trumpeted everywhere and continues to grow. Within the car we have vision, radar and ultrasonic sensors to detect obstacles in front, behind and to the side of the car. Outside the car, V2x promises to share real-time information between vehicles and other sources so we can see ahead of vehicles in front of us, around corners to detect hazards, and see congested traffic and emergency vehicles. Also this AI can improve on the fly, adapting to new conditions through training updates from the cloud. 

Topics: SoC semiconductor automotive automotive functional safety ArterisIP ISO 26262 compliance artificial intelligence AI semiwiki kurt shuler noc interconnect cache coherence SOTIF (ISO 21448 UL 4600

Semiconductor Engineering: Where Should Auto Sensor Data Be Processed?

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:

Where Should Auto Sensor Data Be Processed?

August 1st, 2019 - By Ann Steffora Mutschler

Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...

 

Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.

“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC autonomous driving ArterisIP FlexNoC semiconductor engineering LIDAR noc interconnect cache coherence hardware accelerators

SemiWiki: ML and Memories: A Complex Relationship

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:

ML and Memories: A Complex Relationship

March 13th, 2019 - By Bernard Murphy

How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.

No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.

For more information, please visit the Arteris IP AI package webpage: http://www.arteris.com/flexnoc-ai-package

Topics: semiconductor artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect cache coherence