Arteris Articles

Bernard Murphy of (SemiWiki) comments on a recent book release on MPSoC design. 

Arteris IP Contributes to Major MPSoC Text

April 29th, 2021 - Bernard Murphy

Kurt Shuler, VP of Marketing at Arteris IP updates Bernard Murphy (SemiWiki) on how trends in AI and safety are changing the design considerations for smart features in our cars in this new blog:

Trends in AI and Safety for Cars

February 3rd, 2020 - By Bernard Murphy

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:

Where Should Auto Sensor Data Be Processed?

August 1st, 2019 - By Ann Steffora Mutschler

Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...

Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.

“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:

ML and Memories: A Complex Relationship

March 13th, 2019 - By Bernard Murphy

How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.

No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.