Arteris Articles

SemiWiki: CEO Interview: Charlie Janac of Arteris IP

Charlie Janac, president and CEO at Arteris IP interviewed by Daniel Nenni in this new SemiWiki blog:

CEO Interview: Charlie Janac

August 28, 2020 - By Daniel Nenni

Why is on-chip interconnect important for SoC innovation?
System-on-chip architectures are rapidly changing because we are moving from “data processing” chips to SoCs able to execute “decision making” models. The on-chip interconnect is the logical and physical means to create the SoC architecture so the importance of the network-on-chip (NoC) interconnect has increased as the need for architectural innovation has grown.

What developments do you see that Arteris IP is able to address?
We’re at a very exciting time because an important ingredient for performant SoCs has clearly become the on-chip interconnect and all the SoC architectural changes by our customers are influencing our technology development.

Topics: SoC network-on-chip semiconductor automotive Ncore cache coherency FlexNoC networks AI semiwiki charlie janac noc interconnect ceo data processing superscalers

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

SystemC Gurus Wanted! Arteris IP is Hiring Performance Modeling Engineers

Featured Position!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team creating products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

We are growing our Performance Team to develop models for our next generation product.

Topics: AXI OCP ASIC design cache coherency system level modeling SystemC arteris ip SoCs noc interconnect job CHI

Arteris IP is Hiring!

Performance Modeling Engineer
in Campbell, CA or Austin, TX

Would you like to be part of a team contributing to products that will be used in the next-generation of advanced smartphones, automobiles and other computing devices?

Topics: AXI OCP ASIC design cache coherency arteris ip hardware SoCs noc interconnect job