Arteris Articles

Semiconductor Engineering: The High But Often Unnecessary Cost Of Coherence

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new with Semiconductor Engineering article:

The High But Often Unnecessary Cost Of Coherence

December 22nd, 2021 - By Brian Bailey

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?

“Coherence is a contract between agents that says, ‘I promise you that I will always provide the latest data to you,'” says Michael Frank, fellow and system architect at Arteris IP. “It is mostly important when you have a lot of people sharing the same data set. Coherence between equal peers is very important and will not go away.”

Topics: network-on-chip FPGAs cache coherency artificial intelligence semiconductor engineering arteris ip bandwidth CPUs SoCs accelerators dataflow NoCs Arteris IP (AIP) on-chip cache

Semiconductor Engineering: NoCs In Authoritative MPSoC Reference

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoCs In Authoritative MPSoC Reference

May 6th, 2021 - By Kurt Shuler

The role of the network-on-chip in ensuring total system safety.

K. Charles Janac, president and CEO of Arteris IP, authored the first chapter in that third section on network-on-chip (NoC) architecture and how it has enabled MPSoCs. 

The chapter starts with the evolution from buses to crossbars to NoCs. Next is a useful overview of a typical approach to architecting and configuring a NoC. As the most configurable intellectual property (IP) in an SoC, getting the design to an optimal solution requires careful planning and refinement. The design evolves, not just the logic but also the topology.

By the way, this book is a technical review, not a marketing pitch. Charlie is quite open that while NoCs share some concepts with “regular” communications networks, the analogy cannot be stretched too far. NoC design is still very much an activity for semiconductor designers, not general network designers.

Topics: SoC NoC functional safety network-on-chip ECC cache coherency IEEE semiconductor engineering arteris ip ASIL D K. Charles Janac interconnects kurt shuler ai accelerators security TMR MPSOC LBIST

SemiWiki: CEO Interview: Charlie Janac of Arteris IP

Charlie Janac, president and CEO at Arteris IP interviewed by Daniel Nenni in this new SemiWiki blog:

CEO Interview: Charlie Janac

August 28, 2020 - By Daniel Nenni

Why is on-chip interconnect important for SoC innovation?
System-on-chip architectures are rapidly changing because we are moving from “data processing” chips to SoCs able to execute “decision making” models. The on-chip interconnect is the logical and physical means to create the SoC architecture so the importance of the network-on-chip (NoC) interconnect has increased as the need for architectural innovation has grown.

What developments do you see that Arteris IP is able to address?
We’re at a very exciting time because an important ingredient for performant SoCs has clearly become the on-chip interconnect and all the SoC architectural changes by our customers are influencing our technology development.

Topics: SoC network-on-chip semiconductor automotive Ncore cache coherency FlexNoC networks AI semiwiki charlie janac noc interconnect ceo data processing superscalers

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.


This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free;

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips