Arteris Articles

Semiconductor Engineering: Productivity Keeping Pace With Complexity

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Productivity Keeping Pace With Complexity

September 25th, 2020 - By Brian Bailey

Without productivity gains, design size and complexity would face huge headwinds. Those gains come from a diverse set of improvements.

Nobody doubts the power of reuse. Intellectual Property blocks are either built into a library for those inside of large companies, or if you’re a small company, you go outside and you buy it,” says Benoit de Lescure, CTO for Arteris IP. “Complexity is managed through a divide and conquer strategy. Companies are also using larger macro functions that you stitch together with the same amount of people. Today, you can buy a multiple CPU block, with Level 3 cache, and complex cache coherent interconnect. These have been designed to be easy to configure, and so you can create a very large CPU complex with 8 or 16 CPUs, and that becomes the macro functions you’re integrating.”

Topics: SoC NoC automotive cache coherent interconnect semiconductor engineering soc architecture CPUs Benoit de Lescure verification noc interconnect ML/AI IP market

Arteris and Synopsys Webinar Held on Wednesday, 26 September

synopsys_color_600pxHolger Keding (Synopsys' Solutions Architect), Rocco Jonack (Arteris' Senior Solutions Architect) and Malte Doerper (Synopsys' Product Marketing) will be jointly hosting this webinar,
"Optimization of Cache Coherent Interconnects for Artificial Intelligence SoCs",
on Wednesday, 26 September, at 10 am Pacific time.

Topics: Synopsys cache coherent interconnect artificial intelligence SoCs webinar architect

New EE Times article on Automotive SoCs and Interconnect IP

EE Times just published a new article I wrote about how the automotive industry has replaced the mobile phone industry as the driver for new semiconductor technologies.

Read now: "Mission Critical in Auto SoC: Interconnect IP"

 

Topics: Arteris FlexNoC Ncore eetimes cache coherent interconnect

Arteris Ncore Cache Coherent Interconnect IP Featured in Linley Group Paper

Arteris' Ncore Cache Coherent Interconnect IP was featured in a Linley Group white paper titled, "Easing Heterogeneous Cache Coherent SoC Design using Arteris’ Ncore Interconnect."

Topics: white paper download Ncore cache coherent interconnect The Linley Group