Arteris Articles

Semiconductor Engineering: Steep Spike For Chip Complexity And Unknowns

K. Charles Janac, CEO at Arteris IP is quoted in this new Semiconductor Engineering article:

Steep Spike For Chip Complexity And Unknowns

May 5th, 2021 - By Ed Sperling

Increased interactions and customizations drive up risk of re-spins or failures.

“There are several aspects that need to be considered, such as making sure the customer is using the right version of the IP,” said K. Charles Janac, chairman and CEO of Arteris IP. “You’re basically enforcing that the IP-XACT parameters are there in order for the IP block to be admitted into the SoC. There’s also the aspect of supply management. Many of these companies have a layout house, a design house, and foundry contractors. If that entire supply chain is IP-XACT — from the interaction between the various parties in the supply chain to what ultimately provide what goes into the SoC — it gets much, much smoother. At the same time, you are going to have some pieces of the chip that are on the leading-edge process and some on the trailing edge, such as analog.

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip K. Charles Janac ip-xact interconnects chiplets inter-chip IPD

Semiconductor Engineering: Many Chiplet Challenges Ahead

Michael Frank, fellow and system architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Many Chiplet Challenges Ahead

April 12th, 2021 - By Brian Bailey

Assembling systems from physical IP gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

“The size of the bits and pieces is an issue,” says Michael Frank, fellow and system architect at Arteris IP. “It is perhaps less of an issue with chiplets or 2.5D, where things are mounted on a substrate, but it adds additional challenges for 3D. We are no longer dealing with gravel. It is grains of sand, or even dust specs. It’s more robust to build boards.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip interconnects chiplets Michael Frank 5nm ESD

Semiconductor Engineering: More Data Drives Focus On IC Energy Efficiency

Michael Frank, fellow and system architect at Arteris IP are quoted in this new Semiconductor Engineering article:

More Data Drives Focus On IC Energy Efficiency

April 8th, 2021 - By Ann Steffora Mutschler

Decisions that affect how, when, and where data gets processed.

"On the chip side, it’s an engineering discipline. On the other side are the algorithm experts who understand what the masks are and what they want to do,” said Michael Frank, fellow and system architect at Arteris IP.

Topics: SoC NoC network-on-chip machine learning neural networks semiconductor engineering arteris ip interconnects chiplets Michael Frank memory architecture TensorFlow

Semiconductor Engineering: Roaring '20s For The Chip Industry

Isabelle Geday, Vice President and General Manager for the IP Deployment Division at Arteris IP is quoted in today's Semiconductor Engineering blog:

Roaring '20s For The Chip Industry

January 28th, 2021 - By Brian Bailey

New markets, different architectures, and continued virtual work environments all point to positive and sustained growth.

These advanced technologies are changing the fabric of the industry. “Foundries will keep offering more and more design services,” says Isabelle Geday, vice president and general manager for the IP Deployment Division of Arteris IP. “They will become super design houses to help integration within the value chain for many system houses and Tier 2 IC companies.”

Topics: SoC NoC network-on-chip semiconductor engineering AI chiplets EDA Isabelle Geday IP Deployment Division china start ups chip industry design houses cpu hardware ip