Arteris Articles

EDN: The Network-on-Chip Interconnect is the SoC

Benoit de Lescure, CTO at Arteris IP authors this new series of articles in EDN:

The Network-on-Chip Interconnect is the SoC

March 25th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

“The network is the computer,” coined by John Gage of Sun Microsystems back in 1984, proved incredibly insightful. This idea is re-emerging, this time within the SoC realm. Functions in a chip that communicate with each other—not through simple wires but through complex network elements such as switches, protocol converters, packetizers, and so on—are not so different from the set of computers communicating through a network within a cabinet, or a room, back in 1984.

Topics: SoC NoC AMBA network-on-chip automotive CPU AI arteris ip interconnects QoS DDR ic design EDN bus fabric

Semiconductor Engineering: Von Neumann Is Struggling

Michael Frank, Fellow and System Architect at Arteris IP is quoted in today's Semiconductor Engineering blog:

Von Neumann Is Struggling

January 18th, 2021 - By Brian Bailey

The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architecture.

“One of the problems is that CPUs are not really good at anything,” says Michael Frank, fellow and system architect at Arteris IP. “CPUs are good at processing a single thread that has a lot of decisions in it. That is why you have branch predictors, and they have been the subject of research for many years.”

Topics: SoC Interconnect NoC network-on-chip memory CPU neural networks semiconductor engineering accelerators chip architectures

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC cache coherent IP CPU Ncore semiwiki cache CodaCache on-chip memory performance multi-processor systems congestion configurability last level cache scratchpad way partitioning

CES 2016: CPU, GPU or … VPU?

Winners, losers and observations from the Consumer Electronics Show

Where is the semiconductor industry going in the post-smartphone era? What trends are going to shape next-generation applications and SoC development?

Just by walking around the CES show floor this year, I would say advanced visual processing technology is the horse to put money on. It was everywhere, from ADAS systems, drones, to GoPro cameras, IP cameras with embedded facial recognition, motion detectors, virtual reality, augmented reality, displays and a whole lot more.

Topics: automotive semiconductors ADAS CPU GPU video