Arteris Articles

Semiconductor Engineering: The High But Often Unnecessary Cost Of Coherence

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new with Semiconductor Engineering article:

The High But Often Unnecessary Cost Of Coherence

December 22nd, 2021 - By Brian Bailey

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?


“Coherence is a contract between agents that says, ‘I promise you that I will always provide the latest data to you,'” says Michael Frank, fellow and system architect at Arteris IP. “It is mostly important when you have a lot of people sharing the same data set. Coherence between equal peers is very important and will not go away.”

Topics: network-on-chip FPGAs cache coherency artificial intelligence semiconductor engineering arteris ip bandwidth CPUs SoCs accelerators dataflow NoCs Arteris IP (AIP) on-chip cache

Semiconductor Engineering: What Is An XPU?

Michael Frank, Fellow and System Architect at Arteris IP is quoted throughout this new article in Semiconductor Engineering:

What Is An XPU? 

November 11th, 2021 - By Brian Bailey

Almost every letter of the alphabet has been used to describe a processor architecture, but under the hood they all look very similar.


“Most of these things are not really a processor in the sense of being a CPU,” says Michael Frank, fellow and system architect at Arteris IP. “They’re more like a GPU, an accelerator for a special workload, and there is quite a bit of diversity within them. Machine learning is a class of processors, and you just call them all machine learning accelerators, yet there is a large variety of the part of the processing they accelerate.”


Topics: network-on-chip GPU semiconductor engineering arteris ip CPUs SoCs accelerators DSP Michael Frank NoCs Arteris IP (AIP)

Semiconductor Engineering: NoC Experiences From The Trenches

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoC Experiences From The Trenches

September 28th, 2021 - By Kurt Shuler

When evaluating a new technology, don't aim for a simple 1-to-1 replacement.


Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of attempting a 1-to-1 replacement of their old technology without considering all the new things the new capabilities bring to them.

Read on for some examples I have seen during my years at Arteris IP and check out our customer list, which includes the best-of-the-best in many domains implementing small to large designs.

Topics: Interconnect network-on-chip crossbar automotive FlexNoC semiconductor engineering arteris ip CPUs SoCs RTL kurt shuler chip design NoCs AI designs floorplanning

Semiconductor Engineering: Software-Hardware Co-Design Becomes Real

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

Software-Hardware Co-Design Becomes Real

September 27th, 2021 - By Brian Bailey

Automatic mapping of software onto existing hardware, or using software to drive hardware design, are highly desired but very difficult.


“Hardware/software co-design has been happening for quite a while,” says Michael Frank, fellow and system architect at Arteris IP. “People have been trying to estimate the behavior of the platform and evaluation its performance using real software for quite a while. The industry has been building better simulators, such as Gem5, and Qemu. This has extended into systems where accelerators have been included, where you build models of accelerators and offload your CPUs by running parts of the code on the accelerator."

Topics: Interconnect automotive semiconductor engineering arteris ip CPUs SoCs chip design AI/ML Michael Frank Gem5