Arteris Articles

Semiconductor Engineering: Productivity Keeping Pace With Complexity

Benoit de Lescure, CTO at Arteris IP is quoted in this new article in Semiconductor Engineering:

Productivity Keeping Pace With Complexity

September 25th, 2020 - By Brian Bailey

Without productivity gains, design size and complexity would face huge headwinds. Those gains come from a diverse set of improvements.

Nobody doubts the power of reuse. Intellectual Property blocks are either built into a library for those inside of large companies, or if you’re a small company, you go outside and you buy it,” says Benoit de Lescure, CTO for Arteris IP. “Complexity is managed through a divide and conquer strategy. Companies are also using larger macro functions that you stitch together with the same amount of people. Today, you can buy a multiple CPU block, with Level 3 cache, and complex cache coherent interconnect. These have been designed to be easy to configure, and so you can create a very large CPU complex with 8 or 16 CPUs, and that becomes the macro functions you’re integrating.”

Topics: SoC NoC automotive cache coherent interconnect semiconductor engineering soc architecture CPUs Benoit de Lescure verification noc interconnect ML/AI IP market

SemiWiki: Safety in the Interconnect

Kurt Shuler, VP of Marketing at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

Safety in the Interconnect

 

April 26th,  2018 - By Bernard Murphy

Bernard Murphy (SemiWiki) provides his take on a talk by Kurt Shuler how safety assurance extends to the interconnect, particular challenges in meeting ISO 26262 requirements for highly configurable IP and how Arteris IP addresses these challenges for users of their NoC systems.

Topics: SoC on-chip interconnect networks CPUs GPUs FMEA NIU system safety assurance semiwiki critical safety BIST