Arteris Articles

Semiconductor Engineering: NoC Experiences From The Trenches

Kurt Shuler, Vice President of Marketing at Arteris IP authored this new article in Semiconductor Engineering:

NoC Experiences From The Trenches

September 28th, 2021 - By Kurt Shuler

When evaluating a new technology, don't aim for a simple 1-to-1 replacement.


Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition or who maybe do not yet see a need for a change. As with a switch to any new technology, the first hurdles are often simply misconceptions. When new users first evaluate any new technology, they often make the mistake of attempting a 1-to-1 replacement of their old technology without considering all the new things the new capabilities bring to them.

Read on for some examples I have seen during my years at Arteris IP and check out our customer list, which includes the best-of-the-best in many domains implementing small to large designs.

Topics: Interconnect network-on-chip crossbar automotive FlexNoC semiconductor engineering arteris ip CPUs SoCs RTL kurt shuler chip design NoCs AI designs floorplanning

EDN: How NoCs Ace Power Management and Functional Safety in SoCs

Benoit de Lescure, CTO at Arteris IP authors this 3rd article in a new series for EDN:

How NoCs Ace Power Management and Functional Safety in SoCs

September 15th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

This third article highlights how NoC technology provides capabilities like power management and functional safety that are not possible with older crossbar-based interconnect technologies. For design teams creating modern SoCs, whether large datacenter AI accelerators or power-sipping IoT sensors, NoC interconnect technology is key to implementing these SoC architectures and optimizing the dataflow within them.

To catch up on the first and second articles in this series, click below:

Topics: ARM NIC-400 SoC NoC functional safety network-on-chip crossbar automotive AI arteris ip Benoit de Lescure interconnects EDN LBIST Design Management Power Management Semiconductors DVSF

SemiWiki: Interconnect Basics: Wires to Crossbar to NoC

Kurt Shuler shares with Bernard Murphy an introduction to interconnect topologies, a useful primer to anyone who thinks of interconnect as “just wires” in this new SemiWiki blog:

Interconnect Basics: Wires to Crossbars to NoC

August 21, 2020 - By Bernard Murphy

To many of us, if we ever think about interconnect on an SoC, we may think delay, power consumption, congestion, that sort of thing. All important points from an implementation point of view, but what about the functional and system implications? In the early days, interconnect was very democratic, all wires more or less equal, connecting X to Y wherever needed. If you had a data bus, you’d route that more carefully to ensure roughly equal delays for each bit, which works pretty well when you don’t have a lot of on-chip functions. But there’s more to it than that. This blog is a quick introduction to interconnect basics.

Topics: SoC network-on-chip crossbar semiconductor Ncore FlexNoC networks AI semiwiki kurt shuler noc interconnect NoC layer

The SoC Interconnect Fabric: A Brief History

The high functional integration of system-on-chip designs today is driving the need for new technological approaches in semiconductor design. Anyone who owns a Samsung Galaxy S4, HTC One or comparable smartphone can see the benefits of integrating onto one chip all the computing functions that were traditionally separate, discrete chips on a PC computer motherboard. For next-generation devices, developers are driving even greater computing power, higher resolution graphics, and improved media processing into the integrated SoCs that enable these systems. This high level of integration is causing on-chip communications and transaction handling to become a system constraint within the SoC, limiting the achievable performance of SoCs no matter how optimized the individual CPU, GPU and other IP blocks.

Topics: NoC network-on-chip bus crossbar history