Arteris Articles

Semiconductor Engineering: The High But Often Unnecessary Cost Of Coherence

Michael Frank, Fellow and System Architect at Arteris IP is quoted in this new with Semiconductor Engineering article:

The High But Often Unnecessary Cost Of Coherence

December 22nd, 2021 - By Brian Bailey

Cache coherency is expensive and provides little or negative benefit for some tasks. So why is it still used so frequently?


“Coherence is a contract between agents that says, ‘I promise you that I will always provide the latest data to you,'” says Michael Frank, fellow and system architect at Arteris IP. “It is mostly important when you have a lot of people sharing the same data set. Coherence between equal peers is very important and will not go away.”

Topics: network-on-chip FPGAs cache coherency artificial intelligence semiconductor engineering arteris ip bandwidth CPUs SoCs accelerators dataflow NoCs Arteris IP (AIP) on-chip cache

Semiconductor Engineering: Have Processor Counts Stalled?

Michael Frank, Fellow and Chief Architect at Arteris IP quoted in this new article in Semiconductor Engineering:

Have Processor Counts Stalled?

September 24th, 2020 - By Brian Bailey

Have chips reached a plateau for the number of processor cores they can effectively make use of? Possibly yes, until you change the programming model.

“The number of processors has stalled in platforms like PCs or portable devices,” says Michael Frank, fellow and system architect at Arteris IP. “This has less to do with Moore’s Law leveling out than the fact that it’s getting very hard, from a software point of view, to find enough work for more processors. Unless you have highly parallel workloads, it is really really hard to keep all these cores busy.”

Topics: SoC NoC automotive multicore semiconductor engineering soc architecture noc interconnect ML/AI high-performance dataflow IP market processor cores

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

Abstract:
The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow