Arteris Articles

EDN: Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

Benoit de Lescure, CTO at Arteris IP authors this 2nd article in a new series for EDN:

Why The Network-on-Chip Has Displaced Crossbar Switches at Scale

May 13th, 2021 - By Benoit de Lescure

The NoC interconnect is the SoC architecture.

In my first article of this series about interconnect design, I explained why on-chip communication has become central to a system-on-chip (SoC) architecture. These architectural decisions determine bandwidth, throughput, quality-of-service (QoS), power usage, safety, and cost. Here, the difference between a world-class achievement and a shortcoming starts with the communication architecture choice.

Topics: ARM NIC-400 SoC NoC network-on-chip automotive mobileye AI arteris ip Benoit de Lescure digital eyeq interconnects communications EDN plug-and-play

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO