Arteris Articles

Semiconductor Engineering: Interconnects Emerge As Key Concern For Performance

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Interconnects Emerge As Key Concern For Performance

September 3rd, 2020 - By Ed Sperling

Complexity, abundant options, and limits on tooling make this an increasingly challenging area. 

“On the AI side of things, the architecture is being determined by the capabilities of the interconnect,” said Kurt Shuler, vice president of marketing at Arteris IP . “It’s not just about the individual processing elements. It’s how do you get data between the processing elements and a whole bunch of local memories. In a lot of these AI chips, for power as well as latency and bandwidth, they want to limit as much as possible going off to DRAM, which means you’ve got to do the processing in situ within the chip. You can think of the interconnect as knobs and dials of what you’re capable of doing within these huge AI chips.”
 
Topics: SoC NoC NoC technology semiconductor engineering soc architecture DRAM AI chips noc interconnect IP market

Semiconductor Engineering: What Happened To Execute-In-Place?

Michael Frank, Fellow and Chief Architect at Arteris IP is quoted in this new article in Semiconductor Engineering:

What Happened To Execute-In-Place?

August 25th, 2020 - By Bryon Moyer

The concept as it was originally conceived no longer applies. Here’s why.

“Demand-paging virtual memory is nothing else than a cache,” noted Michael Frank, fellow and chief architect at Arteris IP . But then Android came available for free, unlike the planned OSes. So the strategy changed from one of demand-paging to moving the entire code base from flash to DRAM, and then using the SRAM cache mechanism to further manage instruction access times — all in the interest of lower cost.
 
Frank also stated, “My definition of execute in place is where you do not have an address change, where you execute in a cached way, and your original source of the code or the data is still at the same address that you are executing at.”
 
Topics: SoC NoC technology semiconductor engineering soc architecture AI cache DRAM noc interconnect IP market SRAM MCUs