Arteris Articles

Semiconductor Engineering: What Is An XPU?

Michael Frank, Fellow and System Architect at Arteris IP is quoted throughout this new article in Semiconductor Engineering:

What Is An XPU? 

November 11th, 2021 - By Brian Bailey

Almost every letter of the alphabet has been used to describe a processor architecture, but under the hood they all look very similar.


“Most of these things are not really a processor in the sense of being a CPU,” says Michael Frank, fellow and system architect at Arteris IP. “They’re more like a GPU, an accelerator for a special workload, and there is quite a bit of diversity within them. Machine learning is a class of processors, and you just call them all machine learning accelerators, yet there is a large variety of the part of the processing they accelerate.”


Topics: network-on-chip GPU semiconductor engineering arteris ip CPUs SoCs accelerators DSP Michael Frank NoCs Arteris IP (AIP)

Semiconductor Engineering: Firmware Skills Shortage

Benoit de Lescure, CTO at Arteris IP is quoted in this new Semiconductor Engineering article:

Firmware Skills Shortage

February 25th, 2021 - By Brian Bailey

Adding intelligence into devices requires a different skill set, and finding enough qualified people is becoming a challenge — especially in less glamorous areas.

“I was working in the image compression domain 20 years ago,” says Benoit de Lescure, CTO for Arteris IP. “We had a similar issue, both with off-the-shelf DSP, and our own specialized DSP. Finding people to make efficient use of the SIMD hardware was extremely difficult, because you need to ‘think parallel’. But few people are ready to deep-dive into a hardware architecture that might be obsolete two or three years from now.”

Topics: SoC NoC network-on-chip semiconductor engineering arteris ip Benoit de Lescure DSP SIMD

All About Circuits: The Role of Last-Level Cache Implementation for SoC Developers

Kurt Shuler, vice president of marketing at Arteris IP authored this new All About Circuits article:

The Role of Last-Level Cache Implementation for SoC Developers

May 13th, 2020 - By Kurt Shuler

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

So, what’s the best memory solution? For hints, we can look at what other companies are doing. Tear-down analyses have shown that Apple, for one, solves the speed mismatch problem by adding another cache. If a big company with nearly infinite R&D resources designs around its SoCs bottlenecks this way, it’s probably worth looking into. 
 
Topics: Apple SoC NoC technology CodaCache last level cache kurt shuler noc interconnect ML IP market security All About Circuits DSP